Concurrent Statements

In the following sections we will examine the concept of concurrency as it is implemented in the VHDL language and in VHDL simulators. We will also explore some of the concurrent language features of VHDL in more detail and learn how combinational and registered logic can be described using these features. In addition, we will look briefly at how timing delays are annotated to concurrent assignments in VHDL, so you will have a better understanding of how simulation models are constructed.

  The Concurrent Area

  Concurrent Signal Assignments

  Conditional Signal Assignment

  Selected Signal Assignment

  Conditional vs. Selected Assignment

  Procedure Calls

  Generate Statements

  Concurrent Processes

  Component Instantiations

  Port and Generic Mapping

  Delay Specifications

  Signal Drivers

See also

  Sequential Statements

  Blocks