Delay Specifications

VHDL allows signal assignments to include delay specifications, in the form of an after clause. The after clause allows you to model the behavior of gate and wire delays in a circuit. This is very useful if you are developing simulation models or if you want to include estimated delays in your synthesizable design description. The following are two examples of delay specifications associated with signal assignments:

Y1 <= not (A and B) after 7 ns;

Y2 <= not (A and B) transport after 7 ns;

These two assignments demonstrate the two fundamental types of delay specifications available in VHDL: inertial and transport.

Inertial delay is intended to model the delay through a gate, in which there is some minimum pulse length that must be maintained before an event is propogated.

Transport delay, on the other hand, models the delay on a wire, so pulses of any width are propogated.

For design descriptions intended for synthesis, you will probably not bother to use delay specifications such as these. A circuit produced as a result of synthesis is unlikely to have timing characteristics that can be accurately predicted (or specified) up front. In fact, all synthesis tools in use as of this writing ignore the after clause completely. (If you have a general idea of the timing characteristics of your synthesis target—be it an FPGA chip or a high-complexity ASIC—you can use delay specifications to improve the accuracy of your initial simulation. Just be aware that anything you annotate prior to synthesis will be little more than a guess.)

When you are writing test benches, you will also probably not use after clauses to specify timing of input events. Instead, you will likely rely on a series of wait statements entered within a process to accurately specify your test stimulus.

The IEEE 1076-1993 standard added an additional feature called a reject time. For inertial delays (the default delay type if transport is not specified), a minimum inertial pulse time can be specified as follows:

Y1 <= reject 3 ns not (A and B) after 7 ns;

In this example, any event greater than 3 ns in width will be propagated to the output. In the absence of a specified reject time, the specified delay time (in this case 7 ns) is used as the default reject time.