Sequential Statements
Sequential VHDL statements allow you to describe the operation, or behavior, of your circuit as a sequence of related events. Such descriptions are natural for order-dependent circuits such as state machines and for complex combinational logic that involves some priority of operations. The use of sequential statements to describe combinational logic implies that our use of the term sequential in VHDL is somewhat different from the term as it is often used to describe digital logic. Specifically, sequential statements written in VHDL do not necessarily represent sequential digital logic circuits. As we will see, it is possible (and quite common) to write sequential VHDL statements, using processes and subprograms, to describe what is essentially combinational logic.
In this chapter we will look at examples of both registered logic and combinational logic described using sequential statements. We will also examine the various types of sequential statements available in VHDL. Our primary focus will be on those styles of sequential VHDL that are most appropriate for synthesizable design descriptions and for test benches. We will also touch on issues related to delay specifications and the order in which processes are analyzed—issues closely related to sequential VHDL.
Sequential statements are found within processes, functions, and procedures. Sequential statements differ from concurrent statements in that they have order dependency. This order dependency may or may not imply a sequential circuit (one involving memory elements).
Sequential Statements in Subprograms