If-Then-Else Statements

VHDL includes a variety of control statements that can be used to describe combinational functions, indicate priorities of operations, and specify other high-level behavior.

The if-then-else construct is the most common form of control statement in VHDL. The general form of the if-then-else construct is:

if first_condition then

statements

elsif second_condition then

statements

else

statements

end if;

The conditions specified in an if-then-else construct must evaluate to a Boolean type. This means that the following example is incorrect:

procedure Mux(signal A, B, S: in std_logic; signal O: out std_logic) is

begin

if S then -- Error: S is not Boolean!

O <= B;

else

O <= A;

end if;

end Mux;

Instead, this example must be modified so that the if statement condition evaluates to a Boolean expression:

if S = '1' then -- Now it will work...

O <= B;

else

O <= A;

end if;

end Mux;

The statement parts of an if-then-else construct can contain any sequential VHDL statements, including other if-then-else statement constructs. This means that you can nest multiple levels of if-then-else statements, in the following form:

if outer_condition then

statements

else

if inner_condition then

statements

end if;