How to choose between a conditional assignment and a selected assignment?  Consider this: a conditional assignment always enforces a priority on the conditions. For example, the conditional expression:

 

Q1 <= "01" when A = '1' else

          "10" when B = '1' else

          "11" when C = '1' else

          "00";

 

is identical to the selected assignment:

 

    with std_logic_vector'(A,B,C) select

         Q2 <= "01" when "100",

               "01" when "101",

               "01" when "110",

               "01" when "111",

               "10" when "010",

               "10" when "011",

               "11" when "001",

               "00" when others;

 

Notice that input A takes priority. In the conditional assignment, that priority is implied by the ordering of the expressions. In the selected assignment, you must specify all possible conditions, so there can be no priority implied.

 

Why is this important for synthesis? Consider a circuit in which we know in advance that only one of the three inputs (A, B, or C) could ever be active at the same time. Or perhaps we don't care what the output of our circuit is under the condition where more than one input is active. In such cases, we can reduce the amount of logic required for our design by eliminating the priority implied by the conditional expression. We could instead write our description as:

 

with std_logic_vector'(A,B,C) select

         Q2 <= "01" when "100",

                   "10" when "010",

                   "11" when "001",

                   "00" when others;

 

This version of the description will, in all likelihood, require less logic to implement than the earlier version. This kind of optimization can save dramatic amounts of logic in larger designs.

 

In summary, while a conditional assignment may be more natural to write, a selected signal assignment may be preferable to avoid introducing additional, unwanted logic in your circuit.

 

Other notes

•    You must include all possible conditions in a selected assignment. If not all conditions are easily specified, you can use the others clause as shown above to provide a default assignment.

•    The selection expressions may include ranges and multiple values. For example, you could specify ranges for a bit_vector selection expression as follows:

 

  with Address select

        CS <= SRAM when 0x"0000" to 0x"7FFF",                          PORT when 0x"8000" to 0x"81FF",

                    UART when 0x"8200" to 0x"83FF",

                    PROM when others;

 

•    VHDL `93 adds the following feature to the selected signal assignment: You can use the keyword unaffected to specify that the output does not change under one or more conditions. For example, a multiplexer with two selector inputs could be described as:

 

  with Sel select

          Y <= A when "00",

               B when "01",

               C when "10",

               unaffected when others;

 

Synthesis Note: The preceding multiplexer description may result in a latch being generated from synthesis. This is because the synthesized circuit will have to maintain the value of the output Y when the value of input Sel is "11".