Selected Signal Assignment
A selected signal assignment is similar to a conditional signal assignment but differs in that the input conditions specified have no implied priority. The following is an example of a selected signal assignment:
entity my_mux is
port (Sel: in std_logic_vector (0 to 1);
A, B, C, D: in std_logic_vector (0 to 3);
Y: out std_logic_vector (0 to 3));
end my_mux;
architecture mux1 of my_mux is
begin
with Sel select
Y <= A when "00",
B when "01",
C when "10",
D when others;
end mux1;
In this simple multiplexer example, the selected signal assignment has exactly the same function as the conditional signal assignment presented earlier. This is not always the case, however, and you should carefully evaluate which type of assignment is most appropriate for a given application.
See also
