Generate Statements

Generate statements are provided as a convenient way to create multiple instances of concurrent statements, most typically component instantiation statements. There are two basic varieties of generate statements.

The for-generate statement

The following example shows how you might use a for-generate statement to create four instances of a lower-level component (in this case a RAM block):

architecture generate_example of my_entity is

    component RAM16X1

        port(A0, A1, A2, A3, WE, D: in std_logic;

                O: out std_logic);

    end component;

begin

    . . .

    RAMGEN: for i in 0 to 3 generate

        RAM: RAM16X1 port map ( . . . );

    end generate;

    . . .

end generate_example;

When this generate statement is evaluated, the VHDL compiler will generate four unique instances of component RAM16X1. Each instance will have a unique name that is based on the instance label provided (in this case RAM) and the index value.

For-generate statements can be nested, so it is possible to generate multi-dimensional arrays of component instances or other concurrent statements.

The if-generate statement

The if-generate statement is most useful when you need to conditionally generate a concurrent statement. A typical example of this occurs when you are generating a series of repetitive statements or components and need to supply different parameters, or generate different components, at the beginning or end of the series. The following example shows how a combination of a for-generate statement and two if-generate statements can be used to describe a 10-bit parity generator constructed of cascaded exclusive-OR gates:

library ieee;

use ieee.std_logic_1164.all;

entity parity10 is

    port(D: in std_logic_vector(0 to 9);

            ODD: out std_logic);

    constant width: integer := 10;

end parity10;

library gates;

use gates.all;

architecture structure of parity10 is

    component xor2

        port(A,B: in std_logic;

             Y: out std_logic);

    end component;

    signal p: std_logic_vector(0 to width - 2);

begin

    G: for I in 0 to (width - 2) generate

        G0: if I = 0 generate

             X0: xor2 port map(A => D(0), B => D(1), Y => p(0));

        end generate G0;

        G1: if I > 0 and I < (width - 2) generate

             X0: xor2 port map(A => p(i-1), B => D(i+1), Y => p(i));

        end generate G1;

        G2: if I = (width - 2) generate

             X0: xor2 port map(A => p(i-1), B => D(i+1), Y => ODD);

        end generate G2;

    end generate G;

end structure;