Concurrent Processes

Process statements contain sequential statements but are themselves concurrent statements within an architecture. In most VHDL design descriptions, there are multiple processes that execute concurrently during simulation and describe hardware that is inherently concurrent in its operation.

In the following example, two processes are used to describe a background clock (process CLOCK) and a sequence of stimulus inputs in a test bench:

architecture Stim1 of TEST_COUNT4EN is

component COUNT4EN

port ( CLK,RESET,EN : in std_logic;

COUNT : out std_logic_vector(3 downto 0)

);

end component;

constant CLK_CYCLE : Time := 20 ns;

signal CLK,INIT_RESET,EN : std_logic;

signal COUNT_OUT : std_logic_vector(3 downto 0);

begin

U0: COUNT4EN port map ( CLK=>CLK,RESET=>INIT_RESET,

EN=>EN, COUNT=>COUNT_OUT);

process begin

CLK <= ‘1’;

wait for CLK_CYCLE/2;

CLK <= ‘0’;

wait for CLK_CYCLE/2;

end process;

process begin

INIT_RESET <= ‘0’; EN <= ‘1’;

wait for CLK_CYCLE/3;

INIT_RESET <= ‘1’;

wait for CLK_CYCLE;

INIT_RESET <= ‘0’;

wait for CLK_CYCLE*10;

EN <= ‘0’;

wait for CLK_CYCLE*3;

EN <= ‘1’;

wait;

end process;

end Stim1;

The interrelationships between multiple processes in a design description can be complex. They are discussed in the section Sequential Statements. For the purpose of understanding concurrency, however, you must never assume that any process you write will be executed in simulation prior to any other process. This means that you cannot count on signals or shared variables being updated between two processes.