Component Instantiations

Component instantiations are statements that reference lower-level components in your design, in essence creating unique copies (or instances) of those components. A component instantiation statement is a concurrent statement, so there is no significance to the order in which components are referenced. You must, however, declare any components that you reference in either the declarative area of the architecture (before the begin statement) or in an external package that is visible to the architecture.

The following example demonstrates how component instantiations can be written. In this example, there are two lower-level components (half_adder and full_adder) that are referenced in component instantiations to create a total of four component instances. When simulated or synthesized, the four component instances (A0, A1, A2 and A3) will be processed as four independent circuit elements. In this example, we have declared the two lower-level components half_adder and full_adder right in the architecture. To make your design descriptions more concise, you may choose to place component declarations in separate packages instead.

library ieee;

use ieee.std_logic_1164.all;

entity adder4 is

port(A,B: in std_logic_vector(3 downto 0);

S: out std_logic_vector(3 downto 0);

Cout: out std_logic);

end adder4;

architecture structure of adder4 is

component half_adder

port (A, B: in std_logic; Sum, Carry: out std_logic);

end component;

component full_adder

port (A, B, Cin: in std_logic; Sum, Carry: out std_logic);

end component;

signal C: std_logic_vector(0 to 2);

begin

A0: half_adder port map(A(0), B(0), S(0), C(0));

A1: full_adder port map(A(1), B(1), C(0), S(1), C(1));

A2: full_adder port map(A(2), B(2), C(1), S(2), C(2));

A3: full_adder port map(A(3), B(3), C(2), S(3), Cout);

end structure;