Concurrent Signal Assignments

The most common and simple concurrent statements you will write in VHDL are concurrent signal assignments. Concurrent signal assignments such as those shown in the previous section specify the logical relationships between different signals in a digital system.

If you have used PLD-oriented design languages (such as PALASM, ABEL, CUPL or Altera’s AHDL), then concurrent signal assignments will be quite familiar to you. Just like the Boolean equations that you write using a PLD language, concurrent signal assignments in VHDL describe logic that is inherently parallel.

Because all signal assignments in your design description are concurrent (including those described within processes, as we will see in the next chapter), there is no relevance to the order in which the assignments are made within the concurrent area of the architecture.

In most cases, you will use concurrent signal assignments to describe either combinational logic (using logic expressions of arbitrary complexity), or you will use them to describe the connections between lower-level components. In some cases (though not typically for designs that will be synthesized) you will use concurrent signal assignments to describe registered logic as well.

The following example includes two simple concurrent signal assignments that represent NAND and NOR operations:

architecture arch3 of nand_circuit is

signal A, B: std_logic;

signal Y1, Y2: std_logic;

begin

Y1 <= not (A and B);

Y2 <= not (A or B);

end arch3;

In this example (as in the example presented earlier), there is no significance to the order in which the two assignments have been made. Also, keep in mind that the two signals being assigned (Y1 and Y2) could just as easily have been ports of the entity rather than signals declared in the architecture. In all cases, signals declared locally (within an architecture, for example) can be used in exactly the same ways as can ports of the corresponding entity. The only difference between ports and locally-declared signals is that ports have a direction, or mode (in, out or inout), limiting whether they can have values assigned to them (in the case of in), or whether they can be read as inputs (in the case of out). If a port is declared as mode out, its value cannot be read. It can only be assigned a value. A port of mode in is the opposite; it can be read, but it cannot be assigned a value. A port of mode inout has both capabilities.