The Concurrent Area

In VHDL, there is only one place where you will normally enter concurrent statements. This place, the concurrent area, is found between the begin and end statements of an architecture declaration. The following VHDL diagram shows where the concurrent area of a VHDL architecture is located:

architecture arch1 of my_circuit is

signal Reset, DivClk: std_logic;

constant MaxCount: std_logic_vector(15 downto 0) := "10001111";

component count port (Clk, Rst: in std_logic;

Q: out std_logic_vector(15 downto 0));

begin

Reset <= '1' when Qout = MaxCount else '0';

CNT1: count port map(GClk, Reset, DivClk);

Control: process(DivClk)

begin

. . .

end process;

. . .

end arch1;

All statements within the concurrent area are considered to be parallel in their execution and of equal priority and importance. Processes (described in more detail in Chapter 6, Understanding Sequential Statements) also obey this rule, executing in parallel with other assignments and processes appearing in the concurrent area.

There is no order dependency to statements in the concurrent area, so the following architecture declaration:

architecture arch1 of my_circuit is

signal A, B, C: std_logic_vector(7 downto 0);

constant Init: std_logic_vector(7 downto 0) := "01010101";

begin

A <= B and C;

B <= Init when Select = '1' else C;

C <= A and B;

end arch1;

is exactly equivalent to:

architecture arch2 of my_circuit is

signal A, B, C: std_logic_vector(7 downto 0);

constant Init: std_logic_vector(7 downto 0) := "01010101";

begin

C <= A and B;

A <= B and C;

B <= Init when Select = '1' else C;

end arch2;

The easiest way to understand this concept of concurrency is to think of concurrent VHDL statements as a kind of netlist, in which the various assignments being made are nothing more than connections between different types of objects.

If you think of the signals, constants, components, literals—and even processes—available in concurrent VHDL statements as distinct objects (such as you might find on a schematic or block diagram), and think of operations (such as and, not, and when-else) and assignments as logic gates and wiring specifications, respectively, then you will have no trouble understanding how VHDL's concurrent statements can be mapped to actual digital logic.