Semi-Automated IMINT Processing System (SAIP) Case Study

Abstract

The DARPA Rapid Prototyping of Application Specific Signal Processor (RASSP) program goal was to dramatically reduce the time and effort required to develop, produce, and maintain complex embedded digital signal processing (DSP) systems. Lockheed Martin Advanced Technology Laboratories (ATL) was required to assess the RASSP process improvements by performing design benchmarks. The goal of Benchmark 4 (BM4) was to dramatically upgrade a portion of DARPA's SAIP system using the tools and techniques developed under the RASSP Program. The goal of the upgrade was to increase the processor density by more than 100x while demonstrating the capabilities, benefits and improvements afforded by RASSP's innovative hardware/software codesign methodology.

Purpose

This case study describes in more detail the SAIP application and requirements, the design processes used to develop the BM4 hardware prototype, and the lessons learned and results achieved by applying the RASSP hardware/ software codesign and virtual prototyping techniques, graphical software development and autocoding tools and emerging COTS DSP components. The case study executive summary is divided into the following sections relating more details and insights into the BM4 SAIP HighClass processor development efforts.

Roadmap

1.0 Introduction

2.0 SAIP HighClass Design Problem and Challenges

3.0 The RASSP Development Process Used to Attack the Problem

4.0 The Successes, Setbacks and Results of the SAIP Benchmark Development Effort

Appendix A MSE Classifier Functional Analysis and Implementation
Appendix B HDI Functional Analysis, Optimizations and Implementation Tradeoffs
Appendix C Mean Square Error (MSE) Classifier Custom Board Preliminary Design and Implementation Tradeoffs
Appendix D MSE/MAD Classifier FPGA Custom Board Performance Modeling
Appendix E MSE Classifier C80 and C6201 Custom Board Performance Modeling
Appendix F SAIP HighClass Processor Virtual Prototype Development
Appendix G HDI Data Flow Graph Development and Integration
Appendix H SAIP HighClass Control Program Development and Integration
Appendix I HighClass Prototype Hardware Integration and Test
Appendix J Final System Hardware/Software Integration and Test