Module Declaration
Formal Definition
A module is comprised of the interface and the design behavior.
Simplified Syntax
module | macromodule
identifier (port_list) ;
ports_declaration ;
module_body ;
endmodule
Description
All module declarations must begin with the module
(or macromodule) keyword and
end with the endmodule keyword.
After the module declaration, an identifier is required. A ports
list is an option. After that, ports declaration is given with
declarations of the direction of ports and the optionally type. The
body of module can be any of the following:
-
Any declaration including parameter, function, task, event or any
variable declaration.
-
Continuous assignment.
-
Gate, UDP or module instantiation.
-
Specify block.
-
Initial block
-
Always block.
If there is no instantiation inside the module, it will be treated as
a top-level module
Examples
Example 1
module module_1(a, b, c) ;
parameter size = 3 ;
input [size : 0] a, b ;
output [size : 0] c;
assign c = a & b;
endmodule
Module declaration with a parameter declaration.
Important Notes
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