Methodology Appnote

Abstract

The goal of the Rapid Prototyping of Application-Specific Signal Processors (RASSP) program is to improve by (at least) a factor of four the time required to conceptualize, design/upgrade, and field signal processor systems. Similar improvements in design quality and life-cycle cost were also expected. The overall RASSP methodology is based upon two major beliefs:

• that concurrent design practices, using an integrated approach to hierarchical design verification, are required to improve design quality and performance

• that dramatic (>4X) decreases in cycle time can only be achieved by maximizing reuse of both hardware and software elements.

These two beliefs lead to the notion of design using modular hardware and software functions that are represented in a reuse library. To significantly improve the cycle time and cost of developing signal processing systems, major changes are required in the traditional process. RASSP innovations in the areas of processor architecture selection and verification using Virtual Prototyping and software development using graphical design methods and autocoding have demonstrated the largest contributions to the 4X goals.

In addition to speeding up the individual processes, RASSP reduced a portion of the cycle time by eliminating time-consuming and costly design rework cycles. The RASSP process provides a method to support high-quality designs that lead to first-pass success of all hardware and software elements.

Purpose

This application note serves as the gateway to the other application notes that detail the RASSP developed technologies as well as the case studies that document the actual use of the methodolgy and technologies to specific projects. The following provides a generic description of the process to follow in order to achieve the RASSP benefits. It does not get into the use of the particular tools nor does it provide examples for how to perform designs. These are provided in the Case Studies and Application Notes. By adopting and following the processes described in this document a program will be able to realize the same productivity improvements that Lockheed Martin Advanced Technology Laboratories have demonstrated on the RASSP program.

Roadmap

1.0 Executive Summary

• 1.1 RASSP Methodology Design Process

• 2.1 Objective of this Application Note

• 2.2 Organization of the Application Note

• 2.3 Linkage to other Application Notes

• 3.1 What is a Workflow

• 3.2 Activity Definitions

• 3.3 Workflow Capture
  • 3.3.1 IDEF3X Overview
  • 3.3.2 Precedence Links

• 3.4 Modeling Example

• 3.5 Summary

• 4.1 Iterative Hierarchical Virtual Prototype Process driven by Risk (Spiral Model)

• 4.2 Role of Hardware/Software Codesign

• 4.3 Role of Model Year Architecture

• 4.4 Role of Performance Modeling/Virtual Prototyping

• 4.5 Role of Design For Testability

• 5.1 Overview

• 5.2 Model Year Architecture

• 5.3 Systems Design Process Overview

• 5.4 Architecture Design Process Overview

• 5.5 Detailed Design Process Overview

• 6.1 System Requirements Analysis
  • 6.1.1 System Requirements Development
  • 6.1.2 System Specification Generation
  • 6.1.3 System Requirements Review
• 6.2 System Design Functional Analysis
  • 6.2.1 Functional Identification
  • 6.2.2 Functional Decomposition
  • 6.2.3 Informal Functional Analysis Design Review
• 6.3 System Partitioning
  • 6.3.1 Functional Allocation
  • 6.3.2 Performance Verification
  • 6.3.3 System Design Review
• 6.4 Other Considerations in the System Design Phase
  • 6.4.1 Use of VHDL in System Design Process
  • 6.4.2 Design for Test Tasks in System Design
  • 6.4.3 Role of the Product Development Team in System Design
  • 6.4.4 Design Reviews it System Design Process

7.0 Architecture Design Process Detailed Discussion

• 7.1 Functional Design
  • 7.1.1Architecture Sizing
  • 7.1.2 Selection Criteria Definition
  • 7.1.3 Define Non-DFG/CFG Software Tasks
  • 7.1.4 Flow Graph Generation
  • 7.1.5 Command Program Development
  • 7.1.6 Functional Simulation
• 7.2 Architecture Selection
  • 7.2.1 Architecture Definition
  • 7.2.2 Architecture Model Synthesis
  • 7.2.3 Performance Simulation
  • 7.2.4 Implementation Analysis
  • 7.2.5 Trade-off Analysis
• 7.3 Architecture Verification
  • 7.3.1 Autocode Generation
  • 7.3.2 Performance Simulation
  • 7.3.3 Refine Physical Decomposititon
  • 7.3.4 Refine Implementation Analysis
  • 7.3.5 Model Availability
  • 7.3.6 Verification Approach Definition
  • 7.3.7 Simulation Development
  • 7.3.8 Simulation
  • 7.3.9 Trade-off Analysis Update
• 7.4 Software in Architecture Design Process
  • 7.4.1Domain Primitive
  • 7.4.2 Domain-Primitive Graph
  • 7.4.3 Allocated Graph
  • 7.4.4 Partitioned Software Graph
  • 7.4.5 Partition Graph
  • 7.4.6 Equivalent Application Graph
  • 7.4.7 Command Program
  • 7.4.8 DFG/Command Program Functional Simulation
  • 7.4.9 Non-DFG Software
• 7.5 Other considerations in the Architecture Design Process
  • 7.5.1Use of VHDL in Architecture Process
  • 7.5.2 Design-for-Test Tasks in Architecture Design
  • 7.5.3 Role of PDT in Architecture Process
  • 7.5.4 Design Reviews in Architecture Process

8.0 Detailed Design Process Detailed Discussion

• 8.1 Module/MCM Design Process
  • 8.1.1 Module Preliminary Design
    • 8.1.1.1 Develop Module Behavioral Model
    • 8.1.1.2 Generate Module Test Plan
    • 8.1.1.3 Perform Behavioral Funtional Simulation
    • 8.1.1.4 Generate Module Functional Test Vectors
    • 8.1.1.5 Generate ASIC/FPGA Requirements
    • 8.1.1.6 Search Design Reuse
    • 8.1.1.7 Interactive Logic Design
    • 8.1.1.8 Preliminary Layout (Parts Placement)
    • 8.1.1.9
    • 8.1.1.10 Perform Power/Loading Analysis
    • 8.1.1.11 Perform Functional Timing Simulation
    • 8.1.1.12 Select Parts
    • 8.1.1.13 Generate Production Test Vectors
    • 8.1.1.14 Perform Thermal Analysis
    • 8.1.1.15 Perform Fault Simulation
    • 8.1.1.16 Generate Module Preliminary Design Document
    • 8.1.1.17 Conduct Preliminary Module Design Review
  • 8.1.2 Module Final Design
    • 8.1.2.1 Module Place and Route
    • 8.1.2.2 Udate Module Preliminary Design Document
    • 8.1.2.3 Perform Final Design Functional Timing Simulation
    • 8.1.2.4 Perform Final Design Thermal Analysis
    • 8.1.2.5 Perform Final Design Critical Path Analysis
    • 8.1.2.6 Perform Production Timing Simulation
    • 8.1.2.7 Generate Module Test Procedure and ATE Test Vectors
    • 8.1.2.8 Design and Build Test Adapters
    • 8.1.2.9 Generate Module Artwork and Manufacturing Tools
    • 8.1.2.10 Prepare Module Release Package
    • 8.1.2.11 Conduct Pre-Release Design Review
  • 8.1.3 Hardware Fabrication, Assembly, and Unit Test
• 8.2 ASIC Design Process
  • 8.2.1 ASIC Preliminary Design
  • 8.2.2 ASIC Final Design
  • 8.2.3 ASIC Fabrication and Unit Test
• 8.3 FPGA Design Process
  • 8.3.1 FPGA Preliminary Design
  • 8.3.2 FPGA Final Design
  • 8.3.3 FPGA - Program Device and Unit Test
• 8.4 Backplane Design Process
  • 8.4.1 Backplane Preliminary Design
  • 8.4.2 Backplane Final Design
  • 8.4.3Fabricate, Assemble, and Unit Test Phase
• 8.5 Chassis Design Process
  • 8.5.1 Chassis Preliminary Design
  • 8.5.2 Chassis Final Design
  • 8.5.3 Chassis Fabrication, Assembly, and Unit Test
• 8.6 Subsystem Integration and Test Process
  • 8.6.1 Generate Subsystem Integration Plan
  • 8.6.2 Generate Subsystem Test Plan
  • 8.6.3 Generate Multichassis Test Plan
  • 8.6.4 Generate Chassis Test Plan
  • 8.6.5 Generate Test Procedures for Each Plan
  • 8.6.6 Conduct Test Procedure Review
  • 8.6.7 Integrate Backplanes and Test
  • 8.6.8 Integrate Chassis and Test
  • 8.6.9 Integrate Subsystem and Test
• 8.7 Other Consideration in Detailed Design
  • 8.7.1 Use of VHDL in the Hardware Design Task
  • 8.7.2 Design For Test Tasks in Detailed Design

• 9.1 Software in the Design Process

• 9.2 Hardware/Software Codesign

• 9.3 Library Management

• 9.4 Documentation

10.0 Library Population for Reuse

• 10.1 Signal Processing Primitive Development

• 10.2 Operating System Services Primitive Development

• 10.3 Hardware Model Development

11.0 References