Next: 1.0 Executive Summary Up: Appnotes Index Previous:Appnote Data Flow Graph Index

1.0 Executive Summary

1.1 Overview

1.2 The System Design Process

1.3 The Architecture Design Process

3.0 RASSP Hardware / Software Codesign Process

• 3.1 Definition and Benefits

• 3.2 Implementation of Hardware / Software Codesign in RASSP

• 3.3 HW / SW Codesign Versus Application and Architecture
  • 3.3.1 All COTS Solution

  • 3.3.2 New primitives Required

  • 3.3.3 Custom Hardware Required

• 3.4 Integrated RASSP Architecture Toolset
  • 3.4.1 Implemented Process
    • 3.4.1.1 Architecture Tradeoffs & Mapping Optimization
    • 3.4.1.2 Algorithm Definition & Optimization
    • 3.4.1.3 Testbed Execution & Optimization
    • 3.4.1.4 Command Program Definition & Simulation
    • 3.4.1.5 Target Software Generation and Test

  • 3.4.2 Integrated Toolset
    • 3.4.2.1 GEDAE™ - An Algorithm Development/Autocoding Tool
    • 3.4.2.2 Omniview Cosmos™ - A Performance Modeling Tool
    • 3.4.2.3 ObjectGEODE - A Control Software Development and Autocoding Tool
    • 3.4.2.4 Application Interface Builder

• 4.1 Generating the Data Flow Model

• 4.2 Generating the hardware architecture

• 4.3 Architecture tradeoffs

• 4.4 Control software development

• 5.1 SAR Benchmark Application

• 5.2 Application of Hardware / Software Codesign

• 6.1 Model validation

• 6.2 Simulations must be rapid

• 6.3 Tools must maximize useful information to the designe

• 6.4 New tools and tool interoperability required

• 6.5 Software generation for multiprocessor systems will get easier

• 6.6 Software development paradigm shift is required

• 6.7 Legacy systems

• 7.1 Trademarks and Copyrights

• 7.2 Links to related areas of interest

• 7.3 Articles / Presentations