Next: 3 RASSP Hardware / Software Codesign Process Up: Appnotes Index Previous:1 Executive Summary
Next: 3 RASSP Hardware / Software Codesign Process
Up: Appnotes Index
Previous:1 Executive Summary
2.0 Introduction
This remainder of this Application Note is organized as follows. Section 3 describes the RASSP Hardware / Software Codesign Process and its implementation. Included is a limited discussion of how both the application and an evolving architecture influence the way in which HW/SW Codesign is applied. Section 3 also includes a description of the integrated RASSP architecture toolset with a discussion of both the process implemented and the tools used. Section 4 provides an example of the application of the integrated toolset to the development of an application using a COTS architecture. The example discussed is the Semi-Automated IMINT processor (SAIP) development conducted under Benchmark 4. Section 5 provides an early RASSP example of the codesign process applied to a mixed COTS/Custom architecture. The exmple used in this discussion is the Synthetic Aperture Radar application implemented in the RASSP Benchmark 2. Section 6 discusses some of the lessons learned from the RASSP benchmark developments. Section 7 provides additional information and references.
Next: 3 RASSP Hardware / Software Codesign Process
Up: Appnotes Index
Previous:1 Executive Summary