Research activities

• Digital VLSI design
• VLSI components for spread-spectrum systems
• VHDL Library of Arithmetic Units

Research interests

• Digital VLSI design and synthesis
• Computer arithmetic
• Computer-aided design
• Artificial intelligence

Working position and environment

• Research and teaching assistant on digital VLSI design and Ph.D. student at
• Integrated Systems Laboratory (IIS),
• Department of Electrical Engineering,
• Swiss Federal Institute of Technology (ETH)

Publications

Thesis

• R. Zimmermann, Binary Adder Architectures for Cell-Based VLSI and their Synthesis, PhD thesis, Swiss Federal Institute of Technology (ETH) Zurich, Hartung-Gorre Verlag, 1998.

[abstract, postscript, postscript (letter format)]

Journal papers

• R. Zimmermann and W. Fichtner, ``Low-Power Logic Styles: CMOS Versus Pass-Transistor Logic'', IEEE Journal of Solid-State Circuits, vol. 32, no. 7, pp. 1079-1090, July 1997.

[abstract, postscript]
• R. Zimmermann, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber, and W. Fichtner, ``A 177 Mb/s VLSI Implementation of the International Data Encryption Algorithm'', IEEE Journal of Solid-State Circuits, vol. 29, no. 3, pp. 303-307, March 1994.

[abstract, postscript]
• R. Zimmermann and H. Kaeslin, ``Cell-Based Multilevel Carry-Increment Adders with Minimal AT- and PT-Products'', tried to publish in IEEE Transactions on VLSI Systems but resigned when having to revise it for a second time after a review process of three years!

[abstract, postscript]

Conference papers

• R. Zimmermann, "Efficient VLSI Implementation of Modulo (2^n±1) Addition and Multiplication", to be presented at 14th IEEE Symposium on Computer Arithmetic, Adelaide, Australia, April 14-16, 1999.

[see http://www.ecs.umass.edu/ece/arith14/program.html]
• R. Zimmermann, ``VHDL Library of Arithmetic Units'', in Proc. First Int. Forum on Design Languages (FDL'98), Lausanne, Switzerland, Sept. 1998, pp. 267-272.

[abstract, postscript]
• R. Zimmermann, ``Non-Heuristic Optimization and Synthesis of Parallel-Prefix Adders'', in Proc. Int. Workshop on Logic and Architecture Synthesis (IWLAS'96), Grenoble, France, Dec. 1996, pp. 123-132.

[abstract, postscript]
• R. Zimmermann and R. Gupta, ``Low-Power Logic Styles : CMOS vs CPL'', in Proc. 22nd European Solid-State Circuits Conference (ESSCIRC'96), Neuchâtel, Switzerland, Sept. 1996, pp. 112-115.

[abstract, postscript]

Technical reports / lecture notes

• R. Zimmermann, Computer Arithmetic: Principles, Architectures, and VLSI Design, Lecture notes, Integrated Systems Laboratory, ETH Zürich, 1997.

[contents, postscript, postscript (letter format)]
• R. Zimmermann, ``VHDL Library of Arithmetic Units'', Technical report no. 98/3, Integrated Systems Laboratory, ETH Zürich, Jan. 1998.

[abstract, postscript]
• H. Kunz and R. Zimmermann, ``High-Performance Adder Circuit Generators in Parameterized Structural VHDL'', Technical report no. 96/7, Integrated Systems Laboratory, ETH Zürich, Aug. 1996.

[abstract, postscript]
• R. Zimmermann and M. Neeracher, ``SHIVA: Correlator/Demodulator Chip for Direct-Sequence Spread-Spectrum RAKE-Receiver'', Technical report no. 94/9, Integrated Systems Laboratory, ETH Zürich, May 1994.

[abstract, postscript]

Things to download

• Emacs VHDL Mode Home Page
• VHDL'87 Syntax as HyperText
• VHDL'93 Syntax as HyperText
• Power Calculator for COMPASS

Reto Zimmermann
Integrated Systems Laboratory
ETH-Zentrum
Gloriastrasse 35, ETZ J68
CH-8092 Zürich
Switzerland

phone  : +41 1 632 7786
fax    : +41 1 632 1194
email  : zimmi@iis.ee.ethz.ch
www    : http://www.iis.ee.ethz.ch/~zimmi/