Writing Test Vectors

Another approach to creating test stimuli is to describe the test bench in terms of a sequence of fixed input and expected output values. This sequence of values (sometimes called test vectors) could be described using multi-dimensional arrays or using arrays of records. The following example makes use of a record data type, test_record, which consists of the record elements CE, Set, Din and CRC_Sum. An array type (test_array) is then declared, representing an unconstrained array of test_record type objects. The constant test_vectors, of type test_array, is declared and assigned values corresponding to the inputs and expected output for each desired test vector.

The test bench operation is described using a for loop within a process. This for loop applies the input values Set and Din (from the test record corresponding to the current iteration of the loop) to the unit under test. (The CE input is used within the test bench to enable or disable the clock, and is not passed into the unit under test.) After a certain amount of time has elapsed (as indicated by a wait statement), the CRC_Sum record element is compared against the corresponding output of the unit under test, using an assert statement.

library ieee;

use ieee.std_logic_1164.all;

use work.crc8s;    -- Get the design out of library 'work'

entity testcrc is

end testcrc;

architecture stimulus of testcrc is

    component crc8s

        port (Clk,Set,Din: in std_logic;

              CRC_Sum: out std_logic_vector(15 downto 0));

    end component;

    signal CE: std_logic;

    signal Clk,Set: std_logic;

    signal Din: std_logic;

    signal CRC_Sum: std_logic_vector(15 downto 0);

    signal vector_cnt: integer := 1;

    signal error_flag: std_logic := '0';

    type test_record is record     -- Declare a record type

        CE: std_logic;      -- Clock enable

        Set: std_logic;        -- Register preset signal

        Din: std_logic;        -- Serial Data input

        CRC_Sum: std_logic_vector (15 downto 0);   -- Expected result

    end record;

    type test_array is array(positive range <>) of test_record;  -- Collect them

                -- in an array

    -- The following constant declaration describes the test vectors to be

    -- applied to the design during simulation, and the expected result after a

    -- rising clock edge.

    constant test_vectors : test_array := (

         -- CE, Set, Din, CRC_Sum    

  ('0', '1', '0', "----------------"),  -- Reset

  ('1', '0', '0', "----------------"), -- 'H'

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '0', "0010100000111100"), -- x283C

  ('1', '0', '0', "----------------"), -- 'e'

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '1', "1010010101101001"), -- xA569

  ('1', '0', '0', "----------------"), -- 'l'

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '0', "0010000101100101"), -- x2165

  ('1', '0', '0', "----------------"), -- 'l'

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '0', "1111110001101001"), -- xFC69

  ('1', '0', '0', "----------------"), -- 'o'

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '0', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "----------------"),

  ('1', '0', '1', "1101101011011010")  -- xDADA

    );

begin

    -- instantiate the component

    UUT: crc8s port map(Clk,Set,Din,CRC_Sum);

    -- provide stimulus and check the result

    testrun: process

        variable vector : test_record;

    begin

        for index in test_vectors'range loop

             vector_cnt <= index;

             vector := test_vectors(index);  -- Get the current test vector

          -- Apply the input stimulus...

             CE <= vector.CE;

             Set <= vector.Set;

             Din <= vector.Din;

          -- Clock (low-high-low) with a 100 ns cycle...

             Clk <= '0';

             wait for 25 ns;

             if CE = '1' then

                 Clk <= '1';

             end if;

             wait for 50 ns;

             Clk <= '0';

             wait for 25 ns;

          -- Check the results...

             if (vector.CRC_Sum /= "----------------"

                    and CRC_Sum  /= vector.CRC_Sum) then

                error_flag <= '1';

                assert false

                    report "Output did not match!"

                    severity WARNING;

            else

                error_flag <= '0';

            end if;

        end loop;

        wait;

    end process;

end stimulus;

Note: VHDL 1076-1993 broadened the scope of bit string literals somewhat, making it possible to enter std_logic_vector data in non-binary forms as in the constant hexadecimal value x"283C".