Using Assert Statements

VHDL’s assert statement provides a quick and easy way to check expected values and display messages from your test bench. An assert statement has the following general format:

assert condition_expression

report text_string

severity severity_level ;

When analyzed (either during execution as a sequential statement, or during simulator initialization in the case of a concurrent assert statement), the condition expression is evaluated. As in an if statement, the condition expression of an assert statement must evaluate to a boolean (true or false) value. If the condition expression is false (indicating the assertion failed), the text that you have specified in the optional report statement clause is displayed in your simulator’s transcript (or other) window. The severity statement clause then indicates to the simulator what action (if any) should be taken in response to the assertion failure (or assertion violation, to use the language of the VHDL specification).

The severity level can be specified using one of the following predefined severity levels: NOTE, WARNING, ERROR, or FAILURE. The actions that result from the use of these severity levels will depend on the simulator you are using, but you can generally expect the simulator to display a file name and line number associated with the assert statement, keep track of the number of assertion failures, and print a summary at the end of the simulation run. Assert statements that specify FAILURE in their severity statement clauses will normally result in the simulator halting.