A Simple Test Bench

The simplest test benches are those that apply some sequence of inputs to the circuit being tested (the Unit Under Test, or UUT) so that its operation can be observed in simulation. Waveforms are typically used to represent the values of signals in the design at various points in time. Such a test bench must consist of a component declaration corresponding to the unit under test, and a description of the input stimulus being applied to the UUT.

The following example demonstrates the simplest form of a test bench, and tests the operation of a NAND gate:

library ieee; -- Load the ieee 1164 library

use ieee.std_logic_1164.all; -- Make the package 'visible'

use work.nandgate; -- We'll use the NAND gate model from 'work'

-- The top level entity of the test bench has no ports...

entity testnand is

end testnand;

architecture stimulus of testnand is

-- First, declare the lower-level entity...

component nand

port (A,B: in std_logic;

Y: out std_logic);

end component;

-- Next, declare some local signals to assign values to and observe...

signal A,B: std_logic;

signal Y: std_logic;

begin

-- Create an instance of the comparator circuit...

NAND1: nandgate port map(A => A,B => B,Y => Y);

-- Now define a process to apply some stimulus over time...

process

constant PERIOD: time := 40 ns;

begin

A <= '1';

B <= '1';

wait for PERIOD;

assert (Y = '0')

report "Test failed!" severity ERROR;

A <= '1';

B <= '0';

wait for PERIOD;

assert (Y = '1')

report "Test failed!" severity ERROR;

A <= '0';

B <= '1';

wait for PERIOD;

assert (Y = '1')

report "Test failed!" severity ERROR;

A <= '0';

B <= '0';

wait for PERIOD;

assert (Y = '1')

report "Test failed!" severity ERROR;

wait;

end process;

end stimulus;

Reading from the top of this test bench, we see:

• Library and use statements making the standard logic package available for use (our lower-level NAND gate model has been described using standard logic).

• An optional use statement referencing the lower-level design unit nand from the work library.

• An entity declaration for the test bench. Note that test benches do not generally include an interface (port) list, as they are the highest-level design unit when simulated.

• An architecture declaration, containing:

• A component declaration corresponding to the unit under test.

• Signal declarations for A, B, and Y. These local signals will be used to (1) apply inputs to the unit under test, and (2) observe the behavior or the output during simulation.

• A component instantiation statement and corresponding port map statement that associates the top-level signals A, B and Y with their equivalent ports in the lower-level entity. Note that the component name used (UUT) is not significant; any valid component name could have been chosen.

• A process statement describing the inputs to the circuit over time. This process has been written without the use of a sensitivity list. It uses wait statements to provide a specific amount of delay (defined using constant PERIOD) between each new combination of inputs. Assert statements are used to verify that the circuit is operating correctly for each combination of inputs. Finally, a wait statement without any condition expression is used to suspend simulation indefinitely after the desired inputs have been applied. (In the absence of the final wait statement, the process would repeat forever, or for as long as the simulator had been instructed to run.)