VHDL includes a number of language elements, collectively called objects, that can be used to represent and store data in the system being described. The three basic types of objects that you will use when entering a design description for synthesis or creating functional tests (in the form of a test bench) are signals, variables and constants. Each object that you declare has a specific data type (such as bit or integer) and a unique set of possible values.


The values that an object can take will depend on the definition of the type used for that object. For example, an object of type bit has only two possible values, '0' and '1', while an object of type real has many possible values (floating point numbers within a precision and range defined by the VHDL standard and by the specific simulator you are using).


When an explicit value is specified (such as when you are assigning a value to a signal or variable, or when you are passing a value as a parameter to a subprogram), that value is represented in the form of a literal.


image\diamond.gif  Using Signals

image\diamond.gif  Using Variables

image\diamond.gif  Using Constants and Literals

image\diamond.gif  Understanding Types and Subtypes

image\diamond.gif  Understanding VHDL Operators

image\diamond.gif  Understanding VHDL Attributes

image\diamond.gif  Type Conversions and Type Marks