Variables

Variables are objects used to store intermediate values between sequential VHDL statements. Variables are only allowed in processes, procedures and functions, and they are always local to those functions.

 

Note: The 1076-1993 language standard adds a new type of global variable that has visibility between different processes and subprograms. Global variables are not generally supported in synthesis tools and are not discussed in this book.

 

Variables in VHDL are much like variables in a conventional software programming language. They immediately take on and store the value assigned to them (this is not true of signals, as described in Chapter 6, Understanding Sequential Statements), and they can be used to simplify a complex calculation or sequence of logical operations.

 

The following example is a modified version of the synchronizer circuit presented in the previous section:

 

library ieee;

use ieee.std_logic_1164.all;

entity synch is

    port (Rst, Clk, Grant, nSelect: std_ulogic;

             Request: std_ulogic);

end synch;

 

architecture behavior of synch is

begin

    process(Rst, Clk)

        variable Q1, Q2, Q3: std_ulogic;

    begin

        if Rst = ‘1’ then   -- Async reset

            Q1 := '0'; Q2 := '0'; Q3 := '0';

        elsif (Clk = ‘1’ and Clk’event) then

            Q1 := Grant;

            Q2 := Select;

            Q3 := Q1 and Q3 or Q2;

        end if;

        Request <= Q3;

    end process;

end behavior;

 

In this version of the synchronizer, a single process is again used to describe the behavior of the three commonly-clocked register elements. But in this case, the connections between the three registers are represented by variables that are local to the process, and the result (the output of register Q3) is then assigned to the output port Request. This version of the design will probably not work as intended, because the registered behavior of Q1 and Q2 will be "short circuited" by the fact that variables were used.

 

Because variables do not always result in registers being generated within otherwise clocked processes, you must be very careful when using them. The important distinctions between signals and variables are covered in more detail in a later chapter.