Minimum Register to Register

[Input Pin delay] + [Routing] + [Logic element clock-to-Q] + [Routing] + [Logic Element Delay] + [Routing] + [Logic Element Setup Time]

Dedicated Clkpin

Routing

Clkpin

Logic Element

DFF

Q

DFF

Q

Routing

LUT

D

LUT

Previous slide

Next slide

Back to first slide

View graphic version