Minimum Pin To Pin Delay
[Input Pin delay] + [Logic Element Delay] + [Output Delay]
[Tincomb] + [Tlut + Tcomb] + [Tiod + Tiocomb + Tod1]
What about Routing Delays? Table 20 has routing delays.
Tdin2data - delay from dedicated input or clock to LE data
Tsamecolumn - delay from LE output to IOE in same column
Tsamerow - delay from LE output IOE in same row