Virtex-II Handbook...

 

Devices : Virtex-II Platform FPGAs : Virtex-II Handbook

Virtex-II Handbook

About This Handbook

 137KB

Introduction to the Virtex-II FPGA Family

 103KB

Part 1: Virtex-II Data Sheet

  
  Virtex-II Data Sheet  

Part 2: Virtex-II User Guide: (Entire User Guide)

 11.53MB
 

Chapter 1: Timing Models

 492KB
 

Chapter 2: Design Considerations (includes chapter subsections below)

 3.11MB
    Using Global Clock Networks 313KB
    Using Digital Clock Manager (DCM) 1.17MB
    Using Block SelectRAMTM Memory 296KB
    Using Distributed SelectRAM Memory 307KB
    Using Shift Register Look-Up Tables 183KB
    Designing Large Multiplexers 201KB
    Designing Sum of Products (SOP) 145KB
    Using Embedded Multipliers 185KB
    Using Single-Ended SelectI/O Resources 527KB
    Using Digital Controlled Impedance (DCI) 215KB
    Using DDR I/O 203KB
    Using LVDS I/O 180KB
    Using Bitstream Encryption 155KB
    Using the CORE Generator System 447KB
  Download all VHDL Templates and Sub-Modules 89KB
Download all Verilog Templates and Sub-Modules 72KB

Chapter 3: Configuration

 673KB
 

Chapter 4: PCB Design Considerations (includes subsections below)

 9.93MB
    Pinout Information 149KB
    Pinout Diagrams 1.27MB
    Package Specifications 801KB
    Flip-Chip Packages 801KB
    Thermal Data 84KB
    Printed Circuit Board Considerations 160KB
    Board Routability Guidelines 7.67MB
    Power Consumption 135KB
    IBIS Models 110KB
IBIS Files  
    BSDL and Boundary Scan Models 65KB
BSDL Files  
 

Appendix A: Application Notes (summaries only)

 128KB
    XAPP252: SigmaRAM DDR SRAM Interface for Virtex-II Devices*  
    XAPP253: DDR SDRAM Controller for Virtex-II Devices  
    XAPP254: SiberCAM Interface for Virtex-II Devices  
    XAPP256: FIFOs Using Virtex-II Shift Registers  
    XAPP257: Asynchronous FIFO in Virtex-II Devices*  
    XAPP258: FIFOs Using Virtex-II Block RAM  
    XAPP260: Using Block RAM for High Performance Read/Write CAMs*  
    XAPP261: Data-Width Conversion FIFOs Using Virtex-II Block RAM Memory  
    XAPP262: QDR SRAM Interface for Virtex-II Devices  
    XAPP266: FCRAM Controller for Virtex-II Devices*  
    XAPP267: Parity Generation and Validation in Virtex-II Devices  
    XAPP268: Dynamic Clock Data Alignment*  
    XAPP269: Fast CAM in Virtex-II Devices*  
 

Appendix B: BitGen and PROMGen Switches and Options

 284KB
 

Appendix C: XC18V00 Series PROMs

  
    PROM Package Specifications 280KB
    XC18V00 Series PROM Data Sheet 185KB
 

Appendix D: Glossary

 203KB

* - Full Application Notes coming soon. Abstracts of these items are available now.

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