Flip-Flops
Sometimes the circuits with the goofiest names can do the most amazing things
Hazards
You call this a glitch... I am very disappointed

EE481 Logical Design Lab
Fall 2003, Lab #4

Prelab Questions

  1. Analyze the following circuit:
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  2. Synthesize a D type latch out of a SR flip flops:  The D latch hold its out when clock=1.

  3. Why do we clock flip flops?
  4. Why do use master-slave and/or edge triggered flip flops?
  5. Which type of flip flops' clock scheme would ultimately be the fastest: Master-Slave or Edge Detection? Explain your answer.

Experiments

  1. Implement a SR Flip Flop with SSI gates.
  2. Implement a clocked SR Flip Flop with SSI gates.
  3. Implement a master-slave SR Flip Flop with SSI gates.
  4. Implement the D-FF circuit of Prelab Question 2.
  5. Implement a deboucing circuit using a SR-Flip Flop assumming you will be using a SPDT - single pole double throw switch.

Prelab Questions for Glitches

  1. Show a detailed timing diagram for an XOR gate implemented with NOR gates(show the inputs, all intermediate signals, and the output).
  2. Design a circuit with 1 input and a 1 output where the output will go high permanently if the input ever goes low.
  3. What is the difference between logic and function hazards? If youare given a specific function to implement, which of these can you avoid? How?
  4. What is thedifference between static and dynamic hazards?
  5. Design a circuit that produces a short duration pulse for each pulse(of arbitrary duration) applied to the input.
  6. Design a circuit that will recognize a static hazard.

Experiments: Glitches

  1. Design a circuit that will exhibit a static hazard.
  2. Design a circuit with one output that will oscillate only whenone input is high and the other input is lowin all other cases the output will be high. Demonstrate this circuit and really impress your TA.
  3. Experiment with the longest and shortest oscillation period you can achieve with at most 3 chips from your original parts kit.
  4. What tex2html_wrap_inline42 (one gate delay) are you observing for the 74LSXX chips we use? How does this compare with values you would expect from reading the databook?
  5. Design a circuit that will exhibit a dynamic hazard
  6. Implement a debounce circuit for a mechanical switch.


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