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Testbench is not defined by the VHDL Language Reference Manual and has no formal definition.
entity testbench_ent is
end entity testbench_ent;
architecture testbench_arch of testbench_ent is
signal declarations
component declarations
begin
component instantiations
stimuli (test vectors)
end architecture testbench_arch;
The testbench is a specification in VHDL that plays the role of a complete simulation environment for the analyzed system (unit under test, UUT). A testbench contains both the UUT as well as stimuli for the simulation.
The UUT is instantiated as a component of the testbench and the architecture of the testbench specifies stimuli for the UUT's ports, usually as waveforms assigned to all output and bidirectional ports of the UUT.
The entity of a testbench does not have any ports as this serves as an environment for the UUT. All the simulation results are reported using the assert and report statements.
Example 1
entity Test_Decoder_bcd is
end entity Test_Decoder_bcd;
architecture Struct_1 of
Test_Decoder_bcd is
component Decoder_bcd is
port (
enable : in BIT;
led : in
std_ulogic_vector(3 downto 0);
bcd : out
BIT_VECTOR(1 downto 0));
end component Decoder_bcd;
signal bcd: BIT_VECTOR(1 downto
0) := "11";
signal Enable: BIT := '1';
signal led:
std_ulogic_vector (3 downto 0);
begin
U1: Decoder_bcd port map (Enable,led,bcd);
bcd <= "00" after 5 ns,
"01"
after 15 ns,
"10"
after 25 ns,
"11"
after 35 ns;
assert
bcd = "00" and led = "0001"
or
bcd = "01" and led = "0010"
or
bcd = "10" and led = "0100"
or
bcd = "11" and led = "1000"
report
"There is an incorrect value on the output led"
severity error;
end architecture Struct_1;
The design entity Test_Decoder_BCD is designed to verify correctness
of the Decoder_BCD. This test bench applies stimuli to the bcd inputs
and when the value of the sled signal is other than asingle '1' on
the position corresponding to the binary value of the bcd signal,
with all other bits equal to zero, the listed error is reported.
Testbenches should allow automated verification of the UUT, with reports on success or failure of each sub-test.
In case of sequential units under test, a clock signal should be supported in the testbench. Typically, it is realized as a separate process in the testbench architecture.
In order to stop the simulation with a testbench, stimuli are often specified inside a process which contains a non-conditional wait statement at the end; such statement suspends the execution of the testbench forever.
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