The Synthetic PIC is a Verilog synthesizable model of the PIC 16C5X. It has been synthesized successfully with Synopsys and several ASIC and FPGA libraries. It has some testbench debugging features, and a PERL program to convert MPLAB output to Verilog $readmemh format is included - basically everything you need to start embedding a PIC core in an ASIC/FPGA. Use free tools from Microchip, including assembler and simulator, to develop firmware for your ASIC/FPGA-based version. As always, verification is a continuing activity, so - beware. Use the TESTS.ASM/ROM programs to judge for yourself. I'm currently trying to finish up a new 16C67 version.

last updated 2/16/99

Status: This code changes on a daily basis, but I hope its getting better. I restored the original PIC 4 phases (only 2 are actually active)... It's still synchronous to the one clock. I did this because I'm looking at real memory cells, now, and what I had was too simplified. I'm assuming SYNCHRONOUS memories (you may synthesize the Register File to a read-modidy-write memory and then operate on 1 clock/instruction if your data memory can be small. Email me if you have ideas about this sort of thing, or questions...). I actually modularized the memories in their own file. The register file is greatly simplified. Oh, and forget hex2rom.c. Just use MPLAB's export of the "Disassembled Code" and then a very simple PERL script can translate the code to $readmemh-able format. There's also an INTEL HEX to Verilog converter if you want it.

Special thanks to folks who have found problems and contributed fixes, including: Bill Elliott of Arithmos, Inc.

Source files (ftp files, click and view as text)

• pictest.v...................Top-level testbench module
• piccpu.v...................Top-level cpu module
• picalu.v...................alu module
• picidec.v...................instruction decoder module
• picregs.v...................register file (interface to a synchronous RAM)
• picexp.v...................a simple expansion circuit; shows how to customize
• picdram.v...................('d' is for DATA) memory model for register file (a synchronous RAM)
• picpram.v...................('p' is for PROGRAM) memory model for program memory (a synchronous RAM)
• convert.pl...................PERL script converts MPASM output to $readmemh format
• ihex2vhex.pl...................PERL script converts Intel HEX to $readmemh format (Contributed by Bill Elliott)
• tests.asm...................Several assembler programs for testing the core. They're all mashed together, so you have to seperate manually.

People have asked for the actual .rom files so they can run the testbench as is without having to get the Microchip tools. Obviously, you need to get the Microchip tools at some point, but these files should allow you to run the testbench right away. So, here they are:

• test1.rom
• test2.rom
• test3.rom
• test4.rom
• test5.rom
• test6.rom
• test7.rom
• test8.rom
• test9.rom
• test10.rom

Summary:

This is the next version of the Synthetic PIC I that was VHDL. There are major differences. I intend to support this version over the VHDL version, since I don't use VHDL anymore.... The Verilog version has been taken much further down the synthesizable path.

This is all done in Verilog-XL and Synopsys.

The individual Verilog source files are listed above. The file pictest.v is the testbench that also behaviorally models the program ROM and loads a Verilog memory file ____.ROM. This is a $readmemh compatible file that was derived from the MPASM hex output. Use the PERL program, convert.pl, to go from MPASM to the .rom file (or whatever, it's pretty easy to do).

In terms of synthesizability; I've synthesized it to the LSI Logic 0.5um Standard Cell library and also some new 0.25um libraries. It's about 1500 equivalent gates, not including memories. I haven't done any rigorous synthesis with constraints to see how fast it'll go. Totally unconstrained, I got about 78MHz, so I'm sure with some playing around you can get much much faster.

I'm not producing commercial quality manuals or even quality control - this is just my little project that I hope some people might learn from or reuse. If you want a sophisticated instruction sets - go look at the ARM or the OAK or commercial IP. This is a simple processor that is easily comprehended and easy to work with. Many, many applications require a very simple processor to coordinate the other custom silicon. The PIC is desirable at least because it has a good set of free tools, right from Microchip (inexpensive ones from CCS).

Back to Tom Coonan's Home Page