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The goal of the DARPA/Tri - Service sponsored Rapid Prototyping of Application Specific Signal Processors (RASSP) program is to reduce development and manufacturing time and cost of signal processors by a factor of four. Lockheed Martin Advanced Technology Laboratories' (LM/ATL) RASSP team has developed an integrated systems engineering tool set which forms the basis for a concurrent engineering design environment. This design environment, which consists of Ascent Logic's RDD - 100, PRICE Systems parametric cost estimation models, and Management Sciences RAM - ILS tools, provides the integrated product developmentd team with cost and reliability estimation data within a systems engineering toolset. The concurrent engineering design environment is described and an example is provided which demonstrates the value of the tool integration within the design environment. This design environment enables the integrated product development team to setimate the life-cycle costs and reliability early in the design process.
The RASSP concurrent engineering environment provides the IPDT with the information they need to make decisions early, while making changes is still easy and inexpensive. This environment will allow engineers to make decisions based not only on the current effect of a change, but on the predicted long-term impacts. This information is essential to significantly reducing life-cycle costs.
The RASSP system definition process is a front-end engineering task in which signal processing concepts that meet customer requirements are developed and top-level trade-offs are performed to determine the processing subsystem requirements. Although the same type of functional decomposition and allocation is performed as in the traditional design process, several significant RASSP extensions have been developed which lead to shorter design cycles. Emphasis is placed on understanding the life cycle impact of early design decisions in the RASSP process. Each member of the integrated product development team participates in the system-level tradeoffs to ensure that the complete life cycle is considered during the design process. Model year architecture concepts are used in RASSP designs to ensure that the signal processor can be easily upgraded to support its entire life cycle. Emphasis is placed on making early design decisions so prototyping activities can begin early in the program to reduce high-risk elements. The output of the system definition process is a set of executable specifications that have the requirements for each processing subsystem in an executable form. The executable specifications support the RASSP concept of reuse and minimize errors due to human interpretation. Traceable system requirements are passed via executable specifications from the system definition process to the architecture design process. As the design progresses, the ability to meet requirements is passed back to the system-level simulations so the impact of lower-level trade-offs are analyzed.
The ATL RASSP team selected Ascent Logic Corporation's RDD-100 tool as the central tool of its integrated toolset. This tool provides requirements analysis, functional analysis, and physical decomposition capabilities. It is an Entity, Relationship, Attribute (ERA) database tool with a substantial graphical data entry user interface. RDD-100's database capability enables it to be the primary data storage tool for the tool set. The ATL RASSP Team defined a set database extensions that support the IPDT through the life of a project.
The RDD-100 tool provides the IPDT with three different views of a system: a requirements view, a functional view, and a physical view. The requirements can be related to the functions and the functions can be allocated to the physical architecture. The interrelation of these three views enables users to automatically generate the lower specification documents from the RDD-100 database. The physical view enables cost analysis and reliability and maintainability analyses.
The RDD-100 tool provides the IPDT with three different views of a system: a requirements view, a functional view, and a physical view. The requirements can be related to the functions and the functions can be allocated to the physical architecture. The interrelation of these three views enables users to automatically generate the lower specification documents from the RDD-100 database. The physical view enables cost analysis and reliability and maintainability analyses.
The ATL RASSP team selected a Synthetic Aperture Radar Digital Signal Processor (SAR-DSP) for a trade-off between two different architecture candidates. A preliminary functional analysis was performed to identify the hardware and software needed by each candidate architecture to satisfy the SAR functional requirements. The Candidate 1 architecture uses a mature technology. As shown in Figure 1-5, this architecture consists of a single-board computer (used as a controller), five processor elements (PE1-5), a cross bar, a fiber interface, and a VME Bus. Each processor element contains four separate computational elements (CE1-4). Also shown in Figure 1-5 is the Candidate 2 architecture. This is similar to the first, except that it uses three state-of-the-art processor elements. In addition, PE2 and PE3 contain only two compute elements rather than four.
During the development phase, the trade-off is difficult because a mature technology is less expensive per module and is lower risk, while the state-of-the-art technology has fewer modules, is more compact, and consumes less power.
The following tasks were performed when conducting trade-offs between the candidate architectures.
Architecture 1 |
Architecture 2 |
||||||||||||
Item |
QTY NHA |
Design |
Maturity |
QTY NHA |
Design |
Maturity |
|||||||
Fiber Interface Assembly |
1 |
- |
- |
1 |
- |
- |
|||||||
- Data IO Module |
1 |
New |
Leading Edge |
1 |
New |
Leading Edge |
|||||||
- Fiber Optic Daughter Card |
1 |
COTS |
Mature |
1 |
COTS |
Mature |
|||||||
- FIR Filter Daughter Card |
1 |
NEW |
Leading Edge |
1 |
NEW |
Leading Edge |
|||||||
Host Interface |
1 |
COTS |
Mature |
1 |
COTS |
Mature |
|||||||
Processor Element Assembly |
5 |
- |
- |
3 |
- |
- |
|||||||
- Mother Board |
1 |
COTS |
Leading Edge |
1 |
COTS |
Leading Edge |
|||||||
- CE Daughter Card 1 |
2 |
COTS |
Mature |
1 or 0 |
COTS |
Mature |
|||||||
- CE Daughter Card 2 |
- |
1 |
COTS |
SOA |
|||||||||
Chassis |
1 |
COTS |
Mature |
1 |
COTS |
Mature |
|||||||
Backplane Assembly |
1 |
- |
- |
1 |
- |
- |
|||||||
- VME Backplane |
1 |
COTS |
Mature |
1 |
COTS |
Mature |
|||||||
- Crossbar |
1 |
COTS |
Mature |
1 |
COTS |
Mature |
|||||||
COTS : Commercial of the Shelf SOA : State of the Art QTYNHA: Quantity in Next Higher Assembly |
While generating the equipment/software tree, the following information is populated in the RDD-100 database for each element:
Cost Cycle | Predicted Cost ($M) |
Development Cost | 1.9 |
Production Cost | 95.8 |
Life Cycle Support Cost | 36.9 |
Total Cost | 134.6 |
Cost Cycle | Predicted Cost ($M) |
Development Cost | 2.0 |
Production Cost | 101.0 |
Life Cycle Support Cost | 39.6 |
Total Cost | 142.5 |
With the tools in the concurrent design environment, this information is easily estimated, even during a proposal effort.
Cost Type | Candidate 1 ($K) | Candidate 2 ($K) |
Development Cost | 2.0 | 2.1 |
Production Cost | 101.0 | 89.1 |
Life Cycle Support Cost | 39.6 | 29.8 |
Total Cost | 142.5 | 113.0 |
MTBCF | 2607 hours (Redundancy Required) | 3296 hours (No Redundancy) |
This system design environment quickly provides more detailed and accurate information to the IPDT, and enables them to make better informed decisions early in a system's life cycle and even in the proposal process. Since these early decisions have the largest impact on the overall life-cycle costs of a system, it is important that these decisions be based on all life-cycle costs and not just the cost of the initial development. The tools in this design environment also provide information to support detailed designers throughout the design process.
As shown in the example, it is possible to select the wrong architecture if the decision is only based on the development costs. The life-cycle costs in this example are reduced by over 20% just by understanding these costs early in the development phase. This information is critical in achieving the RASSP goal of a reducing life-cycle costs by a factor of four. The ATL RASSP team is evaluating other technologies to further reduce design-cycle times and costs on the RASSP program.
Although ATL developed the RASSP concurrent system engineering environment to work well in the signal processing domain, many of these concepts can be extended into higher-level systems.