Standard Logic Data Types
This section describes in detail the contents of the IEEE 1164 Standard Logic package std_logic_1164. The std_logic_1164 package is compiled into a library named ieee, and includes the following data type and function definitions:
Type Std_ulogic
Type std_ulogic is intended to represent a single wire that can have various logical (and metalogical) values. Std_ulogic is the base type for other IEEE 1164 (and related) standard types, including std_logic, std_logic_vector, signed and unsigned. Std_ulogic has the following definition:
type std_ulogic is ( 'U',  Uninitialized
'X',  Forcing Unknown
'0',  Forcing 0
'1',  Forcing 1
'Z',  High Impedance
'W',  Weak Unknown
'L',  Weak 0
'H',  Weak 1
''  Don't care
);
The std_ulogic data type is an enumerated type similar is usage to the bit data type provided in the standard (1076) library. Std_ulogic is an unresolved type.
Type Std_ulogic_vector
Type std_ulogic_vector is intended to represent a collection of wires, or a bus of arbitrary width. Std_ulogic_vector has the following definition:
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;
Std_ulogic_vector is an unconstrained array of std_ulogic, and is analogous to the standard type bit_vector.
Type Std_logic
Type std_logic is a resolved type based on std_ulogic, and has the following definition:
subtype std_logic is resolved std_ulogic;
In the case of multiple drivers, the nine values of std_logic are resolved to values as indicated in the chart below.

U 
X 
0 
1 
Z 
W 
L 
H 
 
U 
U 
U 
U 
U 
U 
U 
U 
U 
U 
X 
U 
X 
X 
X 
X 
X 
X 
X 
X 
0 
U 
X 
0 
1 
0 
0 
0 
0 
X 
1 
U 
X 
X 
X 
1 
1 
1 
1 
X 
Z 
U 
X 
0 
1 
Z 
W 
L 
H 
X 
W 
U 
X 
0 
1 
W 
W 
W 
W 
X 
L 
U 
X 
0 
1 
L 
W 
L 
W 
X 
H 
U 
X 
0 
1 
H 
W 
W 
H 
X 
 
U 
X 
X 
X 
X 
X 
X 
X 
X 
Type Std_logic_vector
Std_logic_vector is an unconstrained array of std_logic:
type std_logic_vector is array ( natural range <>) of std_logic;
Subtypes Based on Std_ulogic
subtype X01 is resolved std_ulogic range 'X' to '1';  ('X','0','1')
subtype X01Z is resolved std_ulogic range 'X' to 'Z';  ('X','0','1','Z')
subtype UX01 is resolved std_ulogic range 'U' to '1';  ('U','X','0','1')
subtype UX01Z is resolved std_ulogic range 'U' to 'Z';  ('U','X','0','1','Z')
The X01, X01Z, UX01, and UX01Z subtypes are used within the std_logic_1164 package to simplify various operations on standard logic data, and may also be used when you have a need for 3, 4, or 5valued logic systems.