Configurations

Configurations are features of VHDL that allow large, complex design descriptions to be managed during simulation. (Configurations are not generally supported in synthesis.) One example of how you might use configurations is to construct two versions of a system-level design, one of which makes use of high-level behavioral descriptions of the system components, while a second version substitutes in a post-synthesis timing model of one or more components.

A configuration declaration is a primary design unit that defines the binding of some or all of the component instances in your design description to corresponding lower-level entities and architectures. The configuration declaration can form a simple parts list for your design, or it can be written to contain detailed information about how each component is "wired into" the rest of the design (through specific port mappings) and the values for generics being passed into each entity.

If you think of the configuration declaration as a parts list for your design, you can perhaps visualize it better as follows: consider a design description in which you have described an entity named Board with an architecture named structure. In the architecture structure you have described one instance (U1) of a component called Chip. Moving down in the hierarchy of your design, let's suppose that the entity Chip has been written with four alternative architectures named A1, A2, A3 and A4. (There are many reasons why you might have done this. For example, the default architecture might be the final synthesizable version of the chip, while the remaining three are versions intended strictly for high-level simulation.)

There are many applications of configurations in simulation. For large projects involving many engineers and many design revisions, configurations can be used to manage versions and specify how a design is to be configured for system simulation, detailed timing simulation, and synthesis. Because simulation tools allow configurations to be modified and recompiled without the need to recompile other design units, it is easy to construct alternate configurations of a design very quickly without having to recompile the entire design.

Because configurations are not generally supported in synthesis tools, we will not describe the many advanced uses of configurations for simulation and design management. Instead, you are encouraged to read about them in the VHDL Language Reference Manual (IEEE Standard 1076) or in a book more oriented toward simulation modeling.