VHDL supports many possible styles of design description. These styles differ primarily in how closely they relate to the underlying hardware. When we speak of the different styles of VHDL, we are really talking about the differing levels of abstraction possible using the language—behavior, dataflow, and structure.

 

Suppose the performance specifications for a given project are: "the compressed data coming out of the DSP chip needs to be analyzed and stored within 70 nanoseconds of the strobe signal being asserted..." This human language specification must be refined into a description that can actually be simulated. A test bench written in combination with a sequential description is one such expression of the design. These are all points in the behavior level of abstraction.

 

After this initial simulation, the design must be further refined until the description is something a VHDL synthesis tool can digest. Synthesis is a process of translating an abstract concept into a less-abstract form. The highest level of abstraction accepted by today’s synthesis tools is the dataflow level.

 

The structure level of abstraction comes into play when little chunks of circuitry are to be connected together to form bigger circuits. (If the little chunks being connected are actually quite large chunks, then the result is what we commonly call a block diagram.)  Physical information is the most basic level of all and is outside the scope of VHDL. This level involves actually specifying the interconnects of transistors on a chip, placing and routing macrocells within a gate array or FPGA, etc.

 

Note: In some formal discussions of synthesis, four levels of abstraction are described; behavior, RTL, gate-level and layout. It is our view that the three levels of abstraction presented here provide the most useful distinctions for today’s synthesis user.

 

As an example of these three levels of abstraction, it is possible to describe a complex controller circuit in a number of ways. At the lowest level of abstraction (the structural level), we could use VHDL’s hierarchy features to connect a sequence of predefined logic gates and flip-flips to form the complete circuit. To describe this same circuit at a dataflow level of abstraction, we might describe the combinational logic portion of the controller (its input decoding and transition logic) using higher-level Boolean logic functions and then feed the output of that logic into a set of registers that match the registers available in some target technology. At the behavioral level of abstraction, we might ignore the target technology (and the requirements of synthesis tools) entirely and instead describe how the controller operates over time in response to various types of stimulus.

 

Behavior

The highest level of abstraction supported in VHDL is called the behavioral level of abstraction. When creating a behavioral description of a circuit, you will describe your circuit in terms of its operation over time. The concept of time is the critical distinction between behavioral descriptions of circuits and lower-level descriptions (specifically descriptions created at the dataflow level of abstraction).

 

Examples of behavioral forms of representation might include state diagrams, timing diagrams and algorithmic descriptions.

 

In a behavioral description, the concept of time may be expressed precisely, with actual delays between related events (such as the propagation delays within gates and on wires), or it may simply be an ordering of operations that are expressed sequentially (such as in a functional description of a flip-flop). When you are writing VHDL for input to synthesis tools, you may use behavioral statements in VHDL to imply that there are registers in your circuit. It is unlikely, however, that your synthesis tool will be capable of creating precisely the same behavior in actual circuitry as you have defined in the language. (Synthesis tools today ignore detailed timing specifications, leaving the actual timing results at the mercy of the target device technology.) It is also unlikely that your synthesis tool will be capable of accepting and processing a very wide range of behavioral description styles.

 

If you are familiar with software programming, writing behavior-level VHDL will not seem like anything new. Just like a programming language, you will be writing one or more small programs that operate sequentially and communicate with one another through their interfaces. The only difference between behavior-level VHDL and a software programming language is the underlying execution platform: in the case of software, it is some operating system running on a CPU; in the case of VHDL, it is the simulator and/or the synthesized hardware.

 

Dataflow

In the dataflow level of abstraction, you describe your circuit in terms of how data moves through the system. At the heart of most digital systems today are registers, so in the dataflow level of abstraction you describe how information is passed between registers in the circuit. You will probably describe the combinational logic portion of your circuit at a relatively high level (and let a synthesis tool figure out the detailed implementation in logic gates), but you will likely be quite specific about the placement and operation of registers in the complete circuit.

 

The dataflow level of abstraction is often called register transfer logic, or RTL. This level of abstraction is an intermediate level that allows the drudgery of combinational logic to be simplified (and, presumably, taken care of by logic synthesis tools) while the more important parts of the circuit, the registers, are more completely specified.

 

There are some drawbacks to using a dataflow method of design in VHDL. First, there are no built-in registers in VHDL; the language was designed to be general-purpose, and the emphasis was placed by VHDL’s designers on its behavioral aspects. If you are going to write VHDL at the dataflow level of abstraction, you must first create (or obtain) behavioral descriptions of the register elements you will be using in your design. These elements must be provided in the form of components (using VHDL’s hierarchy features) or in the form

of subprograms (functions or procedures).

 

But for hardware designers, it can be difficult to relate the sequential descriptions and operation of behavioral VHDL with the hardware being described (or modeled). For this reason, many VHDL users, particularly those who are using VHDL as an input to synthesis, prefer to stick with levels of abstraction that are easier to relate to actual hardware devices (such as logic gates and flip-flops). These users are often more comfortable using the dataflow level of abstraction.

 

Structure

The third level of abstraction, structure, is used to describe a circuit in terms of its components. Structure can be used to create a very low-level description of a circuit (such as a transistor-level description) or a very high-level description (such as a block diagram).

 

In a gate-level description of a circuit, for example, components such as basic logic gates and flip-flops might be connected in some logical structure to create the circuit. This is what is often called a netlist. For a higher-level circuit—one in which the components being connected are larger functional blocks—structure might simply be used to segment the design description into manageable parts.

 

Structure-level VHDL features, such as components and configurations, are very useful for managing complexity. The use of components can dramatically improve your ability to re-use elements of your designs, and they can make it possible to work using a top-down design approach.

 

To give an example of how a structural description of a circuit relates to higher levels of abstraction, consider the design of a simple 5-bit counter. To describe such a counter using traditional design methods, we might connect five T flip-flops with some simple decode logic.

 

The following VHDL design description represents this design in the form of a netlist of connected components:

 

entity andgate is

    port(A,B,C,D: in bit := ‘1’; Y: out bit);

end andgate;

 

architecture gate of andgate is

begin

    Y <= A and B and C and D;

end gate;

 

entity tff is

    port(Rst,Clk,T: in bit; Q: out bit);

end tff;

 

architecture behavior of tff is

begin

    process(Rst,Clk)

        variable Qtmp: bit;

    begin

        if (Rst = ‘1’) then

            Qtmp := ‘0’;

        elsif Clk = ‘1’ and Clk’event then

            if T = ‘1’ then

                Qtmp := not Qtmp;

            end if;

        end if;

        Q <= Qtmp;

    end process;

end behavior;

 

entity TCOUNT is

    port (Rst,Clk: in bit;

          Count: out bit_vector(4 downto 0));

end TCOUNT;

 

architecture STRUCTURE of TCOUNT is

    component tff

        port(Rst,Clk,T: in bit; Q: out bit);

    end component;

    component andgate

        port(A,B,C,D: in bit := ‘1’; Y: out bit);

    end component;

    constant VCC: bit := ‘1’;

    signal T,Q: bit_vector(4 downto 0);

 

begin

    T(0) <= VCC;

    T0: tff port map (Rst=>Rst, Clk=>Clk, T=>T(0), Q=>Q(0));

    T(1) <= Q(0);

    T1: tff port map (Rst=>Rst, Clk=>Clk, T=>T(1), Q=>Q(1));

    A1: andgate port map(A=>Q(0), B=>Q(1), Y=>T(2));

    T2: tff port map (Rst=>Rst, Clk=>Clk, T=>T(2), Q=>Q(2));

    A2: andgate port map(A=>Q(0), B=>Q(1), C=>Q(2), Y=>T(3));

    T3: tff port map (Rst=>Rst, Clk=>Clk, T=>T(3), Q=>Q(3));

    A3: andgate port map(A=>Q(0), B=>Q(1), C=>Q(2), D=>Q(3), Y=>T(4));

    T4: tff port map (Rst=>Rst, Clk=>Clk, T=>T(4), Q=>Q(4));

 

    Count <= Q;

 

end STRUCTURE;

 

This structural representation seems a straightforward way to describe a 5-bit counter, and it is certainly easy to relate to hardware since just about any imaginable implementation technology will have the features necessary to implement the circuit. For larger circuits, however, such descriptions quickly become impractical.