FPGA-Embeddable Microcontrollers
with Real-Time JTAG Debugging

FPGA-6805

FPGA-6805 General Description
Available in Verilog netlist form, QuickCores FPGA-6805 is 100% object code compatible with the industry standard 6805. But there are some significant architectural differences which lend QuickCores FPGA-6805 design to implementation in FPGAs. These architectural differences include a three-stage instruction pipeline, single-clock design, and inherent real-time monitor and debugging capability.

Single Clock, Three-Stage Pipeline Design
QuickCores FPGA-6805 architecture is based on a single-clock, three-stage instruction pipeline design and does not use microcode. A single-clock hardware multiplier is optional and if left out of the design to save gates, the core has provisions for asserting an internal NMI line which vectors to interrupt 5 and returns with the result in the A and X register.

Real-Time Monitor and Debug Architecture
QuickCores FPGA-6805 architecture is adapted to include a built-in real-time monitoring a debug capability. The real-time monitor architecture gives the user the ability to examine and edit the 6805's memory and registers on-the-fly and without any software overhead on the target side (since it's all done in hardware). Communication with the core's on-chip debug logic is typically by way of a JTAG connection. Real-time monitoring and debug functions that are supported include: download, examine, edit program/data memory and registers, h/w and s/w breakpoints, single-steps (including real-time single-steps while other processes continue), real-time trace buffer with time-stamp, four-level event sequencing/triggering, event counters, and on/off trace control.

Ideal for Space Applications
QuickCores FPGA-6805 is ideal for space applications for several reasons. First, the FPGA-6805 is tiny. When implemented in an Actel 54SX32A (with no JTAG debug block) the core only takes up about 40% of the available gates and registers. Second, the FPGA-6805 follows the von Neumann model which means that all program and data memory share the same bus and can be readily mapped off-chip thereby freeing up valuable RadHard gates for use in implementing other functions. Third, it's fast. QuickCores FPGA-6805 is from 10 - 20 times faster than the industry standard 6805 which means you can do more.

Download FPGA-6805 CORES
This Verilog netlist is generic in that they can be synthesized with virtually any Verilog synthesis tool including Synplicity, Synopsys and ALTERA's free Quartus II Web Edition software. This core have been implemented successfully in Actel ProASIC^PLUS, ALTERA Cyclone and QuickLogic Eclipse II FPGAs. This core have a built-in, JTAG real-time monitoring and debug capability which is enabled when the "debug.v" module is instantiated in the top level design

파일명: Q6805.zip (47,265 bytes)