Last updated on 10/26/00

The RISC8 a Verilog synthesizable model of a simple 8-bit microcontroller. It is binary code compatible with the Microchip 16C57 microcontroller. A variety of 3rd Party software development tools exist for this architecture making this core attractive for educational purposes or even for use in an FPGA or ASIC (several folks have successfully done this). The core comes with a testbench and some example programs. And again, it is synthesizable. See the on-line manual for more details.

Click here for the PDF version.

Click here for the on-line HTML manual.

Here is the ZIP file containing all the files you need.

Bugs, Notes, Revisions: New ZIP file posted on 10/26/00. Fixed and added the following items:

• Missing FWE in TRI5 instruction
• Removed FWE from OPTION instruction (not needed since OPTION is specifically decoded)
• Generalized PC write so that you can do fancy computed-goto types of things
• Fixed STATUS register update. For example, Clearing STATUS actually now causes Z to be set
• Added a "Hello World" test in preparation for upcoming "User Guide"...

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