Synopsys Synthesizable Intel 8237A DMA Controller

The Intel 8237A is a simple DMA controller. In order to simplify using this controller for educational purposes, many of the advanced features have been removed. A detailed description of what is supported and what is not supported can be found below. The 8237A can be easily incorporated into a design with minimal setup and/or initialization required. The provided design is also synthesizable through Synopsys dc_shell and a testbench is also provided to demostrate the programming and DMA operations.

Supported

Single Transfer Mode
Block Transfer Mode
DMA Channel 0
Read Transfer
Write Transfer

Not Supported

Demand Mode
Cascade Mode
DMA Channels 1-3
Priority
Verify Transfer

Source File Listing

I8237A.vhd
I8237A_TB.vhd
syn.scr
compile.scr

Synthesis Instructions

In order to synthesize the 8237A two script files compile.scr and syn.scr. From within dc_shell enter the following command:

include syn.scr

NOTE: You must change all references of "lsi_10k" to the appropriate synthesis library that you are using.

The output of the synthesis will be two files(I8237A_GATE.vhd and I8237A_GATE.db). The VHDL file can be used to simulate the design at gate-level. The db file can be used to perfrom analysis of the design from within dc_shell without re-synthesizing the design.

You will need to comment out the line(line# 15) that defines the type UNSIGNED in I8237A_GATE.vhd in order to analyze the file properly.

Test Bench

A testbench has been provided that tests programming of the 8237A as well as block transfer operation. It also serves as a guide demonstrating how the 8237A can be used.

Problems And Comments

Please direct any problems and comments to dalton@cs.ucr.edu. We will respond to all inquiries as quick as possible.

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Last Updated 7/15/1999