======================== Chip I8051_ALL-Optimized ======================== Summary Information: -------------------- Type: Optimized implementation Source: I8051_ALL, up to date Status: 0 errors, 0 warnings, 0 messages Export: not exported since last optimization Chip create time: 988.621000s Chip optimize time: 466.571000s Target Information: ------------------- Vendor: Xilinx Family: VIRTEX Device: V300PQ240 Speed: -4 Chip Parameters: ---------------- Optimize for: Speed Optimization effort: Fast Frequency: 50 MHz Is module: No Keep io pads: No Number of flip-flops: 1355 Number of latches: 0 Chip Design Hierarchy: ---------------------- I8051_ALL: defined in C:\WINNT\Profiles\rlopez\Desktop\i8051\i8051_all.vhd I8051_ALU - U_ALU: defined in C:\WINNT\Profiles\rlopez\Desktop\i8051\i8051_alu.vhd I8051_DEC - U_DEC: defined in C:\WINNT\Profiles\rlopez\Desktop\i8051\i8051_dec.vhd I8051_CTR - U_CTR: defined in C:\WINNT\Profiles\rlopez\Desktop\i8051\i8051_ctr.vhd I8051_RAM - U_RAM: defined in C:\WINNT\Profiles\rlopez\Desktop\i8051\i8051_ram.vhd I8051_ROM - U_ROM: defined in C:\WINNT\Profiles\rlopez\Desktop\i8051\i8051_rom.vhd Primitive reference count: -------------------------- BUFGP 1 FD 53 FDC 4 FDCE 166 FDE 1130 FDPE 2 GND 26 I8051_DBG 1 IBUF 41 LUT 4509 MULT_AND 32 MUXCY 2 MUXCY_L 170 MUXF5 1 OBUF_S_12 58 RAMB4_S4 2 VCC 1 XORCY 165 Chip Module Information: ------------------------ Cell Area FlipFlops Latches .................................................................... /I8051_ALL 4509(100%) 1355 0 /I8051_ALL/I8051_ALU - U_ALU 476(10%) 0 0 /I8051_ALL/I8051_DEC - U_DEC 518(11%) 0 0 /I8051_ALL/I8051_CTR - U_CTR 1046(23%) 154 0 /I8051_ALL/I8051_RAM - U_RAM 2469(54%) 1201 0 /I8051_ALL/ - U_DBG 0(0%) 0 0 /I8051_ALL/I8051_ROM - U_ROM 0(0%) 0 0 Clocks: ------- Required Estimated Period Rise Fall Freq Freq Signal (ns) (ns) (ns) (MHz) (MHz) ............................................................... 20 0 10 50.00 n/a default 20 0 10 50.00 11.60 clk_BUFGPed Timing Groups: -------------- Name Description ........................................................................... (I) Input ports (O) Output ports (RC,clk_BUFGPed) Clocked by rising edge of clk_BUFGPed Timing Path Groups: ------------------- Required Estimated Delay Delay From To (ns) (ns) .......................................................................... (I) (RC,clk_BUFGPed) 20.00 37.96 (RC,clk_BUFGPed) (O) 20.00 8.36 (RC,clk_BUFGPed) (RC,clk_BUFGPed) 20.00 86.21 Input Port Timing: ------------------ Required Estimated Port Delay Slack Name (ns) (ns) To-Group ........................................................................... rst -17.96 -17.96 (RC,clk_BUFGPed) clk 19.12 19.12 (RC,clk_BUFGPed) xrm_in_data<7> 10.83 10.83 (RC,clk_BUFGPed) xrm_in_data<6> 10.83 10.83 (RC,clk_BUFGPed) xrm_in_data<5> 10.83 10.83 (RC,clk_BUFGPed) xrm_in_data<4> 10.83 10.83 (RC,clk_BUFGPed) xrm_in_data<3> 8.79 8.79 (RC,clk_BUFGPed) xrm_in_data<2> 8.79 8.79 (RC,clk_BUFGPed) xrm_in_data<1> 8.79 8.79 (RC,clk_BUFGPed) xrm_in_data<0> 8.79 8.79 (RC,clk_BUFGPed) p0_in<7> 8.78 8.78 (RC,clk_BUFGPed) p0_in<6> 8.78 8.78 (RC,clk_BUFGPed) p0_in<5> 8.78 8.78 (RC,clk_BUFGPed) p0_in<4> 8.78 8.78 (RC,clk_BUFGPed) p0_in<3> 8.78 8.78 (RC,clk_BUFGPed) p0_in<2> 8.78 8.78 (RC,clk_BUFGPed) p0_in<1> 8.78 8.78 (RC,clk_BUFGPed) p0_in<0> 8.78 8.78 (RC,clk_BUFGPed) p1_in<7> 6.74 6.74 (RC,clk_BUFGPed) p1_in<6> 6.74 6.74 (RC,clk_BUFGPed) p1_in<5> 6.74 6.74 (RC,clk_BUFGPed) p1_in<4> 6.74 6.74 (RC,clk_BUFGPed) p1_in<3> 6.74 6.74 (RC,clk_BUFGPed) p1_in<2> 6.74 6.74 (RC,clk_BUFGPed) p1_in<1> 6.74 6.74 (RC,clk_BUFGPed) p1_in<0> 6.74 6.74 (RC,clk_BUFGPed) p2_in<7> 4.70 4.70 (RC,clk_BUFGPed) p2_in<6> 4.70 4.70 (RC,clk_BUFGPed) p2_in<5> 4.70 4.70 (RC,clk_BUFGPed) p2_in<4> 4.70 4.70 (RC,clk_BUFGPed) p2_in<3> 4.70 4.70 (RC,clk_BUFGPed) p2_in<2> 4.70 4.70 (RC,clk_BUFGPed) p2_in<1> 4.70 4.70 (RC,clk_BUFGPed) p2_in<0> 4.70 4.70 (RC,clk_BUFGPed) p3_in<7> 6.74 6.74 (RC,clk_BUFGPed) p3_in<6> 6.74 6.74 (RC,clk_BUFGPed) p3_in<5> 6.74 6.74 (RC,clk_BUFGPed) p3_in<4> 6.74 6.74 (RC,clk_BUFGPed) p3_in<3> 6.74 6.74 (RC,clk_BUFGPed) p3_in<2> 6.74 6.74 (RC,clk_BUFGPed) p3_in<1> 6.74 6.74 (RC,clk_BUFGPed) p3_in<0> 6.74 6.74 (RC,clk_BUFGPed) Output Port Timing: ------------------- Required Estimated Port Delay Slack Name (ns) (ns) From-Group ........................................................................... xrm_addr<15> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<14> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<13> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<12> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<11> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<10> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<9> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<8> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<7> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<6> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<5> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<4> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<3> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<2> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<1> 20.00 11.65 (RC,clk_BUFGPed) xrm_addr<0> 20.00 11.65 (RC,clk_BUFGPed) xrm_out_data<7> 20.00 11.65 (RC,clk_BUFGPed) xrm_out_data<6> 20.00 11.65 (RC,clk_BUFGPed) xrm_out_data<5> 20.00 11.65 (RC,clk_BUFGPed) xrm_out_data<4> 20.00 11.65 (RC,clk_BUFGPed) xrm_out_data<3> 20.00 11.65 (RC,clk_BUFGPed) xrm_out_data<2> 20.00 11.65 (RC,clk_BUFGPed) xrm_out_data<1> 20.00 11.65 (RC,clk_BUFGPed) xrm_out_data<0> 20.00 11.65 (RC,clk_BUFGPed) xrm_rd 20.00 11.65 (RC,clk_BUFGPed) xrm_wr 20.00 11.65 (RC,clk_BUFGPed) p0_out<7> 20.00 11.64 (RC,clk_BUFGPed) p0_out<6> 20.00 11.64 (RC,clk_BUFGPed) p0_out<5> 20.00 11.64 (RC,clk_BUFGPed) p0_out<4> 20.00 11.64 (RC,clk_BUFGPed) p0_out<3> 20.00 11.64 (RC,clk_BUFGPed) p0_out<2> 20.00 11.64 (RC,clk_BUFGPed) p0_out<1> 20.00 11.64 (RC,clk_BUFGPed) p0_out<0> 20.00 11.64 (RC,clk_BUFGPed) p1_out<7> 20.00 11.64 (RC,clk_BUFGPed) p1_out<6> 20.00 11.64 (RC,clk_BUFGPed) p1_out<5> 20.00 11.64 (RC,clk_BUFGPed) p1_out<4> 20.00 11.64 (RC,clk_BUFGPed) p1_out<3> 20.00 11.64 (RC,clk_BUFGPed) p1_out<2> 20.00 11.64 (RC,clk_BUFGPed) p1_out<1> 20.00 11.64 (RC,clk_BUFGPed) p1_out<0> 20.00 11.64 (RC,clk_BUFGPed) p2_out<7> 20.00 11.64 (RC,clk_BUFGPed) p2_out<6> 20.00 11.64 (RC,clk_BUFGPed) p2_out<5> 20.00 11.64 (RC,clk_BUFGPed) p2_out<4> 20.00 11.64 (RC,clk_BUFGPed) p2_out<3> 20.00 11.64 (RC,clk_BUFGPed) p2_out<2> 20.00 11.64 (RC,clk_BUFGPed) p2_out<1> 20.00 11.64 (RC,clk_BUFGPed) p2_out<0> 20.00 11.64 (RC,clk_BUFGPed) p3_out<7> 20.00 11.64 (RC,clk_BUFGPed) p3_out<6> 20.00 11.64 (RC,clk_BUFGPed) p3_out<5> 20.00 11.64 (RC,clk_BUFGPed) p3_out<4> 20.00 11.64 (RC,clk_BUFGPed) p3_out<3> 20.00 11.64 (RC,clk_BUFGPed) p3_out<2> 20.00 11.64 (RC,clk_BUFGPed) p3_out<1> 20.00 11.64 (RC,clk_BUFGPed) p3_out<0> 20.00 11.64 (RC,clk_BUFGPed) Critical Path Timing: --------------------- Arrival Required Cell Time Time Fanout Type (ns) (ns) Count Pin-Name ........................................................................ FDE 86.21 20.00 1357 /I8051_ALL-Optimized/U_CTR/alu_src_3_reg<0>/C FDE 85.45 19.24 1 /I8051_ALL-Optimized/U_CTR/alu_src_3_reg<0>/D LUT4 84.15 17.94 1 /I8051_ALL-Optimized/U_CTR/C24335/O LUT4 83.41 17.20 1 /I8051_ALL-Optimized/U_CTR/C24335/I2 LUT3 82.11 15.90 1 /I8051_ALL-Optimized/U_CTR/C24337/O LUT3 81.37 15.16 1 /I8051_ALL-Optimized/U_CTR/C24337/I2 LUT4 80.07 13.86 1 /I8051_ALL-Optimized/U_CTR/C24338/O LUT4 79.33 13.12 8 /I8051_ALL-Optimized/U_CTR/C24338/I3 LUT4 77.82 11.61 8 /I8051_ALL-Optimized/U_CTR/C24671/O LUT4 77.08 10.87 1 /I8051_ALL-Optimized/U_CTR/C24671/I3 LUT4 75.78 9.57 1 /I8051_ALL-Optimized/U_CTR/C24672/O LUT4 75.04 8.83 1 /I8051_ALL-Optimized/U_CTR/C24672/I3 LUT4 73.74 7.53 1 /I8051_ALL-Optimized/U_CTR/C24673/O LUT4 73.00 6.79 2 /I8051_ALL-Optimized/U_CTR/C24673/I3 LUT2 71.69 5.48 2 /I8051_ALL-Optimized/U_CTR/C24706/O LUT2 70.95 4.74 1 /I8051_ALL-Optimized/U_CTR/C24706/I0 LUT4 69.65 3.44 1 /I8051_ALL-Optimized/U_CTR/C24708/O LUT4 68.91 2.70 8 /I8051_ALL-Optimized/U_CTR/C24708/I3 LUT4 67.40 1.19 8 /I8051_ALL-Optimized/U_ALU/C2374/O LUT4 66.66 0.45 10 /I8051_ALL-Optimized/U_ALU/C2374/I0 XORCY 64.98 -1.23 10 /I8051_ALL-Optimized/U_ALU/C550/C11/C1/O XORCY 64.44 -1.77 1 /I8051_ALL-Optimized/U_ALU/C550/C11/C1/CI MUXCY_L 64.44 -1.77 1 /I8051_ALL-Optimized/U_ALU/C550/C10/C2/LO MUXCY_L 64.38 -1.83 2 /I8051_ALL-Optimized/U_ALU/C550/C10/C2/CI MUXCY_L 64.38 -1.83 2 /I8051_ALL-Optimized/U_ALU/C550/C9/C2/LO MUXCY_L 64.32 -1.89 2 /I8051_ALL-Optimized/U_ALU/C550/C9/C2/CI MUXCY_L 64.32 -1.89 2 /I8051_ALL-Optimized/U_ALU/C550/C8/C2/LO MUXCY_L 64.26 -1.95 2 /I8051_ALL-Optimized/U_ALU/C550/C8/C2/CI MUXCY_L 64.26 -1.95 2 /I8051_ALL-Optimized/U_ALU/C550/C7/C2/LO MUXCY_L 64.20 -2.01 2 /I8051_ALL-Optimized/U_ALU/C550/C7/C2/CI MUXCY_L 64.20 -2.01 2 /I8051_ALL-Optimized/U_ALU/C550/C6/C2/LO MUXCY_L 64.14 -2.07 2 /I8051_ALL-Optimized/U_ALU/C550/C6/C2/CI MUXCY_L 64.14 -2.07 2 /I8051_ALL-Optimized/U_ALU/C550/C5/C2/LO MUXCY_L 64.08 -2.13 2 /I8051_ALL-Optimized/U_ALU/C550/C5/C2/CI MUXCY_L 64.08 -2.13 2 /I8051_ALL-Optimized/U_ALU/C550/C4/C2/LO MUXCY_L 63.24 -2.97 2 /I8051_ALL-Optimized/U_ALU/C550/C4/C2/S LUT1 63.24 -2.97 2 /I8051_ALL-Optimized/U_ALU/C2211/O LUT1 62.50 -3.71 1 /I8051_ALL-Optimized/U_ALU/C2211/I0 LUT2 61.20 -5.01 1 /I8051_ALL-Optimized/U_ALU/C550/C4/C0/O LUT2 60.46 -5.75 3 /I8051_ALL-Optimized/U_ALU/C550/C4/C0/I0 LUT3 59.14 -7.07 3 /I8051_ALL-Optimized/U_ALU/C2319/O LUT3 58.40 -7.81 8 /I8051_ALL-Optimized/U_ALU/C2319/I1 XORCY 56.89 -9.32 8 /I8051_ALL-Optimized/U_ALU/C549/C11/C1/O XORCY 56.35 -9.86 1 /I8051_ALL-Optimized/U_ALU/C549/C11/C1/CI MUXCY_L 56.35 -9.86 1 /I8051_ALL-Optimized/U_ALU/C549/C10/C2/LO MUXCY_L 56.29 -9.92 1 /I8051_ALL-Optimized/U_ALU/C549/C10/C2/CI MUXCY_L 56.29 -9.92 1 /I8051_ALL-Optimized/U_ALU/C549/C9/C2/LO MUXCY_L 56.23 -9.98 2 /I8051_ALL-Optimized/U_ALU/C549/C9/C2/CI MUXCY_L 56.23 -9.98 2 /I8051_ALL-Optimized/U_ALU/C549/C8/C2/LO MUXCY_L 56.17 -10.04 2 /I8051_ALL-Optimized/U_ALU/C549/C8/C2/CI MUXCY_L 56.17 -10.04 2 /I8051_ALL-Optimized/U_ALU/C549/C7/C2/LO MUXCY_L 56.11 -10.10 2 /I8051_ALL-Optimized/U_ALU/C549/C7/C2/CI MUXCY_L 56.11 -10.10 2 /I8051_ALL-Optimized/U_ALU/C549/C6/C2/LO MUXCY_L 56.05 -10.16 2 /I8051_ALL-Optimized/U_ALU/C549/C6/C2/CI MUXCY_L 56.05 -10.16 2 /I8051_ALL-Optimized/U_ALU/C549/C5/C2/LO MUXCY_L 55.99 -10.22 2 /I8051_ALL-Optimized/U_ALU/C549/C5/C2/CI MUXCY_L 55.99 -10.22 2 /I8051_ALL-Optimized/U_ALU/C549/C4/C2/LO MUXCY_L 55.15 -11.06 2 /I8051_ALL-Optimized/U_ALU/C549/C4/C2/S LUT1 55.15 -11.06 2 /I8051_ALL-Optimized/U_ALU/C2220/O LUT1 54.41 -11.80 1 /I8051_ALL-Optimized/U_ALU/C2220/I0 LUT2 53.11 -13.10 1 /I8051_ALL-Optimized/U_ALU/C549/C4/C0/O LUT2 52.37 -13.84 3 /I8051_ALL-Optimized/U_ALU/C549/C4/C0/I0 LUT3 51.05 -15.16 3 /I8051_ALL-Optimized/U_ALU/C2325/O LUT3 50.31 -15.90 8 /I8051_ALL-Optimized/U_ALU/C2325/I1 XORCY 48.80 -17.41 8 /I8051_ALL-Optimized/U_ALU/C548/C11/C1/O XORCY 48.26 -17.95 1 /I8051_ALL-Optimized/U_ALU/C548/C11/C1/CI MUXCY_L 48.26 -17.95 1 /I8051_ALL-Optimized/U_ALU/C548/C10/C2/LO MUXCY_L 48.20 -18.01 1 /I8051_ALL-Optimized/U_ALU/C548/C10/C2/CI MUXCY_L 48.20 -18.01 1 /I8051_ALL-Optimized/U_ALU/C548/C9/C2/LO MUXCY_L 48.14 -18.07 2 /I8051_ALL-Optimized/U_ALU/C548/C9/C2/CI MUXCY_L 48.14 -18.07 2 /I8051_ALL-Optimized/U_ALU/C548/C8/C2/LO MUXCY_L 48.08 -18.13 2 /I8051_ALL-Optimized/U_ALU/C548/C8/C2/CI MUXCY_L 48.08 -18.13 2 /I8051_ALL-Optimized/U_ALU/C548/C7/C2/LO MUXCY_L 48.02 -18.19 2 /I8051_ALL-Optimized/U_ALU/C548/C7/C2/CI MUXCY_L 48.02 -18.19 2 /I8051_ALL-Optimized/U_ALU/C548/C6/C2/LO MUXCY_L 47.96 -18.25 2 /I8051_ALL-Optimized/U_ALU/C548/C6/C2/CI MUXCY_L 47.96 -18.25 2 /I8051_ALL-Optimized/U_ALU/C548/C5/C2/LO MUXCY_L 47.90 -18.31 2 /I8051_ALL-Optimized/U_ALU/C548/C5/C2/CI MUXCY_L 47.90 -18.31 2 /I8051_ALL-Optimized/U_ALU/C548/C4/C2/LO MUXCY_L 47.06 -19.15 2 /I8051_ALL-Optimized/U_ALU/C548/C4/C2/S LUT1 47.06 -19.15 2 /I8051_ALL-Optimized/U_ALU/C2230/O LUT1 46.32 -19.89 1 /I8051_ALL-Optimized/U_ALU/C2230/I0 LUT2 45.02 -21.19 1 /I8051_ALL-Optimized/U_ALU/C548/C4/C0/O LUT2 44.28 -21.93 3 /I8051_ALL-Optimized/U_ALU/C548/C4/C0/I0 LUT3 42.96 -23.25 3 /I8051_ALL-Optimized/U_ALU/C2332/O LUT3 42.22 -23.99 8 /I8051_ALL-Optimized/U_ALU/C2332/I1 XORCY 40.71 -25.50 8 /I8051_ALL-Optimized/U_ALU/C547/C11/C1/O XORCY 40.17 -26.04 1 /I8051_ALL-Optimized/U_ALU/C547/C11/C1/CI MUXCY_L 40.17 -26.04 1 /I8051_ALL-Optimized/U_ALU/C547/C10/C2/LO MUXCY_L 40.11 -26.10 1 /I8051_ALL-Optimized/U_ALU/C547/C10/C2/CI MUXCY_L 40.11 -26.10 1 /I8051_ALL-Optimized/U_ALU/C547/C9/C2/LO MUXCY_L 40.05 -26.16 2 /I8051_ALL-Optimized/U_ALU/C547/C9/C2/CI MUXCY_L 40.05 -26.16 2 /I8051_ALL-Optimized/U_ALU/C547/C8/C2/LO MUXCY_L 39.99 -26.22 2 /I8051_ALL-Optimized/U_ALU/C547/C8/C2/CI MUXCY_L 39.99 -26.22 2 /I8051_ALL-Optimized/U_ALU/C547/C7/C2/LO MUXCY_L 39.93 -26.28 2 /I8051_ALL-Optimized/U_ALU/C547/C7/C2/CI MUXCY_L 39.93 -26.28 2 /I8051_ALL-Optimized/U_ALU/C547/C6/C2/LO MUXCY_L 39.87 -26.34 2 /I8051_ALL-Optimized/U_ALU/C547/C6/C2/CI MUXCY_L 39.87 -26.34 2 /I8051_ALL-Optimized/U_ALU/C547/C5/C2/LO MUXCY_L 39.81 -26.40 2 /I8051_ALL-Optimized/U_ALU/C547/C5/C2/CI MUXCY_L 39.81 -26.40 2 /I8051_ALL-Optimized/U_ALU/C547/C4/C2/LO MUXCY_L 38.97 -27.24 2 /I8051_ALL-Optimized/U_ALU/C547/C4/C2/S LUT1 38.97 -27.24 2 /I8051_ALL-Optimized/U_ALU/C2241/O LUT1 38.23 -27.98 1 /I8051_ALL-Optimized/U_ALU/C2241/I0 LUT2 36.93 -29.28 1 /I8051_ALL-Optimized/U_ALU/C547/C4/C0/O LUT2 36.19 -30.02 3 /I8051_ALL-Optimized/U_ALU/C547/C4/C0/I0 LUT3 34.87 -31.34 3 /I8051_ALL-Optimized/U_ALU/C2340/O LUT3 34.13 -32.08 8 /I8051_ALL-Optimized/U_ALU/C2340/I1 XORCY 32.62 -33.59 8 /I8051_ALL-Optimized/U_ALU/C546/C11/C1/O XORCY 32.08 -34.13 1 /I8051_ALL-Optimized/U_ALU/C546/C11/C1/CI MUXCY_L 32.08 -34.13 1 /I8051_ALL-Optimized/U_ALU/C546/C10/C2/LO MUXCY_L 32.02 -34.19 1 /I8051_ALL-Optimized/U_ALU/C546/C10/C2/CI MUXCY_L 32.02 -34.19 1 /I8051_ALL-Optimized/U_ALU/C546/C9/C2/LO MUXCY_L 31.96 -34.25 2 /I8051_ALL-Optimized/U_ALU/C546/C9/C2/CI MUXCY_L 31.96 -34.25 2 /I8051_ALL-Optimized/U_ALU/C546/C8/C2/LO MUXCY_L 31.90 -34.31 2 /I8051_ALL-Optimized/U_ALU/C546/C8/C2/CI MUXCY_L 31.90 -34.31 2 /I8051_ALL-Optimized/U_ALU/C546/C7/C2/LO MUXCY_L 31.84 -34.37 2 /I8051_ALL-Optimized/U_ALU/C546/C7/C2/CI MUXCY_L 31.84 -34.37 2 /I8051_ALL-Optimized/U_ALU/C546/C6/C2/LO MUXCY_L 31.78 -34.43 2 /I8051_ALL-Optimized/U_ALU/C546/C6/C2/CI MUXCY_L 31.78 -34.43 2 /I8051_ALL-Optimized/U_ALU/C546/C5/C2/LO MUXCY_L 31.72 -34.49 2 /I8051_ALL-Optimized/U_ALU/C546/C5/C2/CI MUXCY_L 31.72 -34.49 2 /I8051_ALL-Optimized/U_ALU/C546/C4/C2/LO MUXCY_L 30.88 -35.33 2 /I8051_ALL-Optimized/U_ALU/C546/C4/C2/S LUT1 30.88 -35.33 2 /I8051_ALL-Optimized/U_ALU/C2253/O LUT1 30.14 -36.07 1 /I8051_ALL-Optimized/U_ALU/C2253/I0 LUT2 28.84 -37.37 1 /I8051_ALL-Optimized/U_ALU/C546/C4/C0/O LUT2 28.10 -38.11 3 /I8051_ALL-Optimized/U_ALU/C546/C4/C0/I0 LUT3 26.78 -39.43 3 /I8051_ALL-Optimized/U_ALU/C2349/O LUT3 26.04 -40.17 8 /I8051_ALL-Optimized/U_ALU/C2349/I1 XORCY 24.53 -41.68 8 /I8051_ALL-Optimized/U_ALU/C545/C11/C1/O XORCY 23.99 -42.22 1 /I8051_ALL-Optimized/U_ALU/C545/C11/C1/CI MUXCY_L 23.99 -42.22 1 /I8051_ALL-Optimized/U_ALU/C545/C10/C2/LO MUXCY_L 23.93 -42.28 1 /I8051_ALL-Optimized/U_ALU/C545/C10/C2/CI MUXCY_L 23.93 -42.28 1 /I8051_ALL-Optimized/U_ALU/C545/C9/C2/LO MUXCY_L 23.87 -42.34 2 /I8051_ALL-Optimized/U_ALU/C545/C9/C2/CI MUXCY_L 23.87 -42.34 2 /I8051_ALL-Optimized/U_ALU/C545/C8/C2/LO MUXCY_L 23.81 -42.40 2 /I8051_ALL-Optimized/U_ALU/C545/C8/C2/CI MUXCY_L 23.81 -42.40 2 /I8051_ALL-Optimized/U_ALU/C545/C7/C2/LO MUXCY_L 23.75 -42.46 2 /I8051_ALL-Optimized/U_ALU/C545/C7/C2/CI MUXCY_L 23.75 -42.46 2 /I8051_ALL-Optimized/U_ALU/C545/C6/C2/LO MUXCY_L 23.69 -42.52 2 /I8051_ALL-Optimized/U_ALU/C545/C6/C2/CI MUXCY_L 23.69 -42.52 2 /I8051_ALL-Optimized/U_ALU/C545/C5/C2/LO MUXCY_L 23.63 -42.58 2 /I8051_ALL-Optimized/U_ALU/C545/C5/C2/CI MUXCY_L 23.63 -42.58 2 /I8051_ALL-Optimized/U_ALU/C545/C4/C2/LO MUXCY_L 22.79 -43.42 2 /I8051_ALL-Optimized/U_ALU/C545/C4/C2/S LUT1 22.79 -43.42 2 /I8051_ALL-Optimized/U_ALU/C2266/O LUT1 22.05 -44.16 1 /I8051_ALL-Optimized/U_ALU/C2266/I0 LUT2 20.75 -45.46 1 /I8051_ALL-Optimized/U_ALU/C545/C4/C0/O LUT2 20.01 -46.20 3 /I8051_ALL-Optimized/U_ALU/C545/C4/C0/I0 LUT3 18.69 -47.52 3 /I8051_ALL-Optimized/U_ALU/C2359/O LUT3 17.95 -48.26 8 /I8051_ALL-Optimized/U_ALU/C2359/I1 XORCY 16.44 -49.77 8 /I8051_ALL-Optimized/U_ALU/C544/C11/C1/O XORCY 15.90 -50.31 1 /I8051_ALL-Optimized/U_ALU/C544/C11/C1/CI MUXCY_L 15.90 -50.31 1 /I8051_ALL-Optimized/U_ALU/C544/C10/C2/LO MUXCY_L 15.84 -50.37 1 /I8051_ALL-Optimized/U_ALU/C544/C10/C2/CI MUXCY_L 15.84 -50.37 1 /I8051_ALL-Optimized/U_ALU/C544/C9/C2/LO MUXCY_L 15.78 -50.43 2 /I8051_ALL-Optimized/U_ALU/C544/C9/C2/CI MUXCY_L 15.78 -50.43 2 /I8051_ALL-Optimized/U_ALU/C544/C8/C2/LO MUXCY_L 15.72 -50.49 2 /I8051_ALL-Optimized/U_ALU/C544/C8/C2/CI MUXCY_L 15.72 -50.49 2 /I8051_ALL-Optimized/U_ALU/C544/C7/C2/LO MUXCY_L 15.66 -50.55 2 /I8051_ALL-Optimized/U_ALU/C544/C7/C2/CI MUXCY_L 15.66 -50.55 2 /I8051_ALL-Optimized/U_ALU/C544/C6/C2/LO MUXCY_L 15.60 -50.61 2 /I8051_ALL-Optimized/U_ALU/C544/C6/C2/CI MUXCY_L 15.60 -50.61 2 /I8051_ALL-Optimized/U_ALU/C544/C5/C2/LO MUXCY_L 15.54 -50.67 2 /I8051_ALL-Optimized/U_ALU/C544/C5/C2/CI MUXCY_L 15.54 -50.67 2 /I8051_ALL-Optimized/U_ALU/C544/C4/C2/LO MUXCY_L 14.70 -51.51 2 /I8051_ALL-Optimized/U_ALU/C544/C4/C2/S LUT1 14.70 -51.51 2 /I8051_ALL-Optimized/U_ALU/C2280/O LUT1 13.96 -52.25 1 /I8051_ALL-Optimized/U_ALU/C2280/I0 LUT2 12.66 -53.55 1 /I8051_ALL-Optimized/U_ALU/C544/C4/C0/O LUT2 11.92 -54.29 3 /I8051_ALL-Optimized/U_ALU/C544/C4/C0/I0 LUT3 10.60 -55.61 3 /I8051_ALL-Optimized/U_ALU/C2373/O LUT3 9.86 -56.35 13 /I8051_ALL-Optimized/U_ALU/C2373/I1 XORCY 8.12 -58.09 13 /I8051_ALL-Optimized/U_ALU/C543/C11/C1/O XORCY 7.58 -58.63 1 /I8051_ALL-Optimized/U_ALU/C543/C11/C1/CI MUXCY_L 7.58 -58.63 1 /I8051_ALL-Optimized/U_ALU/C543/C10/C2/LO MUXCY_L 7.52 -58.69 1 /I8051_ALL-Optimized/U_ALU/C543/C10/C2/CI MUXCY_L 7.52 -58.69 1 /I8051_ALL-Optimized/U_ALU/C543/C9/C2/LO MUXCY_L 7.46 -58.75 2 /I8051_ALL-Optimized/U_ALU/C543/C9/C2/CI MUXCY_L 7.46 -58.75 2 /I8051_ALL-Optimized/U_ALU/C543/C8/C2/LO MUXCY_L 7.40 -58.81 2 /I8051_ALL-Optimized/U_ALU/C543/C8/C2/CI MUXCY_L 7.40 -58.81 2 /I8051_ALL-Optimized/U_ALU/C543/C7/C2/LO MUXCY_L 7.34 -58.87 2 /I8051_ALL-Optimized/U_ALU/C543/C7/C2/CI MUXCY_L 7.34 -58.87 2 /I8051_ALL-Optimized/U_ALU/C543/C6/C2/LO MUXCY_L 7.28 -58.93 2 /I8051_ALL-Optimized/U_ALU/C543/C6/C2/CI MUXCY_L 7.28 -58.93 2 /I8051_ALL-Optimized/U_ALU/C543/C5/C2/LO MUXCY_L 7.22 -58.99 2 /I8051_ALL-Optimized/U_ALU/C543/C5/C2/CI MUXCY_L 7.22 -58.99 2 /I8051_ALL-Optimized/U_ALU/C543/C4/C2/LO MUXCY_L 7.16 -59.05 2 /I8051_ALL-Optimized/U_ALU/C543/C4/C2/CI MUXCY_L 7.16 -59.05 2 /I8051_ALL-Optimized/U_ALU/C543/C2/C2/LO MUXCY_L 6.32 -59.89 2 /I8051_ALL-Optimized/U_ALU/C543/C2/C2/S LUT1 6.32 -59.89 2 /I8051_ALL-Optimized/U_ALU/C2291/O LUT1 5.58 -60.63 1 /I8051_ALL-Optimized/U_ALU/C2291/I0 LUT2 4.28 -61.93 1 /I8051_ALL-Optimized/U_ALU/C543/C2/C0/O LUT2 3.54 -62.67 28 /I8051_ALL-Optimized/U_ALU/C543/C2/C0/I0 FDE 1.37 -64.84 28 /I8051_ALL-Optimized/U_CTR/alu_src_1_reg<7>/Q FDE 0.00 -66.21 1357 /I8051_ALL-Optimized/U_CTR/alu_src_1_reg<7>/C