Dalton Project University of California Dept. of Computer Science Riverside, CA 92521 dalton@cs.ucr.edu

Synopsys Simulation for Beginners

1. Analyzing Files
   1. Go to directory where you downloaded the latest i8051 files
      • cd nameofdirectory
   2. Create a directory called "work" in your project directory
      • mkdir work
   3. Analyze each of the files, there are two ways to do this:
      • Analyze each file seperatley, remebering to compile the innermost entities first by using the following commands:
        • vhdlan i8051_lib.vhd
        • vhdlan i8051_alu.vhd
        • vhdlan i8051_dec.vhd
        • vhdlan i8051_ram.vhd
        • vhdlan i8051_rom.vhd
        • vhdlan i8051_ctr.vhd
        • vhdlan i8051_dbg.vhd
        • vhdlan i8051_all.vhd
        • vhdlan i8051_tsb.vhd
      • OR Analyze all the files by using the script file provided which will automatically analyze all the components (making sure that you set the execute permission on the script file)which you can do with the following commands:
        • chmod 700 zsim.scr
        • zsim.scr
2. Tracing Signals
   1. Open the Synopsys VHDL Debugger by typing the following command:
      • vhdldbx
      • Double click on "CFG_I8051_TSB" located in the Design window
   2. Select the signals you want to trace in your entity
      • Click on "Misc" in the Synopsys VHDL Debugger window
      • Click on "Hierarchy Browser" in the pull-down menu
      • In the VSS Hierarchy Browser the arrow points to the top level entity you are simulating
      • Click on the arrow to display the smaller elements that the top level entity is composed of
      • The window to the right shows the signals corresponding to the entity which the arrow points to
      • Continue clicking on the arrows until the right window displays the signal you wish to trace
      • Double click on the signal you want to trace
   3. The Synopsys Waveform Viewer should appear
      • Signals should appear in the Waveform Viewer
      • Click on "View" in the Waveform Viewer.
      • In the drop-down menu click on "Full Name". This will display the name of the signal without all of the clutter.
3. Simulate
   1. Getting your C code ready to simulate (i.e. converting your C file to VHDL ROM model)
      • Compile your C file into Intel hex format (If you are using a KEIL compiler you can follow the steps below)
        • c51 filename.c
        • bl51 filename.obj to filename.abs
        • oh51 filename.abs
      • Convert your hexfile into a VHDL ROM model
        • g++ -Wall i8051_mkr.cc
        • a.out filename.hex
        • a file called i8051_rom.vhd will be generated, copy this into your project directory
        • you will have to re-analyze the files (see above)
   2. In the Synopsys VHDL Debugger
      • enter the time (in nanoseconds) that you want to simulate
      • Click on Run
      • The waveforms will appear in the Synopsys Waveform Viewer