EE 8993 VHDL Modeling Course (Spring 2003)

In terms of course prerequisites, I am assuming that everybody is already familiar with RTL-level VHDL via the Digital System Design course (ECE 4743/6743) or some other source. This object of this course is to introduce the student to more of the VHDL modeling language than what has been covered in previous courses. We will also cover aspects of Verilog which do not overlap VHDL functionality, and look at mixed-mode simulation.

Textbook

From the digital design course you should already have a textbook which talks about many of the features of the language. Because of this, I have assigned the IEEE Standard VHDL Language Reference Manual as the textbook for this course. This is not that readable, but it is the definitive reference for the language. MSU currently has access to IEEE Explore so you can download the entire language reference manual from this site. Our software is compatible with the '-93 language standard - we may talk about some of the '-2000 extensions but will not use anything specific to the '-2000 standard. Either the IEEE Std 1076-1993, -2000, or -2002 standards will work equally well.

Policy

The grading policy will be:

• 45% simulations
• 40% Tests (3 tests)
• 15% Final

All simulations are to be INDIVIDUAL work. You may discuss the assignments with other students but you may not share any code, or show anybody your code as examples of how to do something. Any violations of this policy will result in the assignment of a failing grade for the ENTIRE course.

Links to Course Information

• Course Intro , (PDF) , ZIP archive of class examples
• 'exam1' VHDL example and Intro to Modelsim , (PDF)
• Delay Modeling in VHDL , (PDF)
• Predefined Types, File IO , (PDF)
• IEEE 1164 Standard , PDF
• Simulation #2, Part 1: Variables, FSMs, bidirectional ports , PDF
• Simulation #2, Part 2: Shared Bus operation , PDF
• Type Declarations, Record Types, Packages , PDF
• Example Model: PAL 16L8 , PDF , PLD model
• Sim3: 8 CPU + Arbiter Simulation , PDF
• The numeric_std package, PDF
• Model Efficieny, Representing Databook Timing , PDF , monitor VHDL model , Cypress Dual Port SRAM model
• Simulation #4 - CSMA/CD Protocol simulation , PDF
• Simulation #5 - Intro to Synopsys Synthesis and DesignWare components , PDF
• Synopsys BC Example: Summer , PDF , ZIP archive of all files
• Simulation #6 - DesignWare Synthetic Operators , PDF
• Simulation #7 - Bilinear filter implementation using Behavioral Compiler , PDF
• Psuedo USB Simulation
• Intro to Verilog
• Some Timing issues in Verilog , PDF
• Clifford E. Cummings Paper on Verilog Coding Styles, SNUG Best Paper Award (2000)
• Switch Level Modeling in Verilog , PDF
• DETFF Verilog Simulation (Simulation #8) , PDF
• Verilog RTL (Simulation #9) , PDF
• Synopsys BC 4x4 Multiply Example , ZIP archive of all files
• System C Notes
• Intro to Verilog-AMS , PDF
• Mechanical Systems in Verilog-AMS
• The IBIS Standard

Assignments (Spring 2003)

• Simulation #1 Due Wed, Jan 22, classtime
• Simulation #2 Due Wed, Jan 29 , classtime
• Simulation #3 Assignment, Due Tues, Feb 7, 8:00 am , ZIP archive of model files
• Simulation #4 Assignment, Due Thurs, Feb 17, Classtime , ZIP archive of model files , Submission script
• Simulation #5 - Intro to Synopsys Synthesis and DesignWare components , PDF , dware.zip archive of Synopsys files , dw_test.zip archive of VHDL Testbench files , Due Feb 26th, classtime, Submission script
• Simulation #6 - DesignWare Synthetic Operators , PDF , dsp_dware.zip archive of Synopsys files , dsp_test.zip archive of Modelsim testbench , Due Friday, Mar 7th, Submission script
• Simulation #7 - Bilinear filter implementation using Behavioral Compiler , PDF , dsp_dware.zip archive of Synopsys files , bifilt_test.zip archive of Modelsim testbench , Due Wednesday, Mar 26th, Submission script
• Verilog RTL (Simulation #8) , PDF , ZIP Archive , Due Friday, April 4, Submission script
• Submission script for Verilog AMS Lab

Old Assignments (Spring 2002)

• Simulation #1 Due Thurs, Jan 24 , classtime
• Simulation #2 Due Thurs, Jan 31 , classtime
• Simulation #3 Assignment, Due Tues, Feb 12, Classtime , ZIP archive of model files
• Simulation #4 Assignment, Due Thurs, Feb 21, Classtime , ZIP archive of model files , Submission script
• Simulation #5 - Intro to Synopsys Synthesis and DesignWare components , PDF , dware.zip archive of Synopsys files , dw_test.zip archive of VHDL Testbench files , Due Mar 5th at 5:00 pm, Submission script
• Simulation #6 - DesignWare Synthetic Operators , PDF , dsp_dware.zip archive of Synopsys files , dsp_test.zip archive of Modelsim testbench , Due Thursday, Mar 21th, Submission script
• Simulation #7 - Bilinear filter implementation using Behavioral Compiler , PDF , dsp_dware.zip archive of Synopsys files , bifilt_test.zip archive of Modelsim testbench , Due Wednesday, Mar 28th, Submission script
• Simulation #8 - DETFF Verilog Simulation , PDF , ZIP Archive , Due Thursday, April 4, Submission script
• Verilog RTL (Simulation #9) , PDF ,n ZIP Archive , Due Thursday, April 18, Submission script

Assignments (previous semesters)

• Simulation #1 Assignment, Due Thurs, Jun 7 , classtime
• Simulation #2 Assignment, Due Wed, Jun 13, 5:00
• Simulation #3 Assignment, Due Mon, Jun 25, 5:00
• USB Assignment (Sim #4, Due, Mon Jul 9, 5:00) , Zip archive of USB VHDL files , Submission script
• Verilog Testbench for DETFF Model (Sim #5 ) , Makefile , Submission script ,Due Mon Jul 16th
• Test #2 Makeup, Simulation #6 , Zip Archive for problem #1 ,

Old Tests

• Test #3 Solution, Spring 2003
• Test #2 Solution, Spring 2003
• Test #1 Solution, Spring 2003
• Test #1 Solution, Spring 2002
• Test #1 Solution, Summer 2001
• Test #1 Solution, Summer 1999

VHDL Packages

• Std Logic 1164
• Std Logic Arith
• Std Logic Signed
• Std Logic Unsigned
• Std Logic textio
• numeric_std (used for synthesis of numeric functions)

Email List

The class EMAIL list will be the one provided by Information Technology Services (ITS). The email list is ece8990-03.spring2003@courses.msstate.edu. See the Class EMAIL Faq for further information about how to be added to the list.

WARNING!!! It is your responsibility to make sure that you are on this email list. I will send many homework/test/lecture announcements to this list -- you are responsible for reading the emails sent to this list.

Misc Links

• Verilog LRM Project, Prof. Mike Smith, Univ of Hawaii
• Verilog Intro (Daniel Hyde, Bucknell) Nice tutorial
• Verilog vs VHDL (Douglas J. Smith, Veribest Incorporated) Neutral comparison of the two languages
• Papers on Verilog at Verilog Center
• Verilog Papers by Clifford E. Cummings, Sunburst Design
• Verilog-AMS Examples
• Excellent VHDL-AMS tutorial(DAC 99 )by Ernst Christen, Kenneth Bakalar, Allen M. Dewey, Eduard Moser
• Transmission Line Modeling, Lynne Green
• Validating IBIS Models
• IBIS ANSI/EIA Homepage