Partitioning of Design
Splitting a design over multiple PLDs is called “partitioning”
Number of inputs will not be a concern
- Will be limited by # of FFs, # of outputs
Could we have used just two PLDs? (see next page)
- PLD_A: 3 FFs for Cntr, 3 FFs for FSM, 7 outputs (Cntb[2:0], Win, Lose, Ena, Sp). Could even use one-hot encoding for FSM (3 more FFs, three more outputs).
- PLD_B: 3 FFs for Cntr, 4 FFs for Point Register, 7 outputs (Cnta[2:0], Eq, D7, D11, D2312). But 4 FFs for Cntr consumes 4 outputs so 11 outputs total!!!!
- This division of the logic will not work.
Some other partition of the logic could possibly be found. Three PLDs gives good observation of internal signal values.