12
VHDL code reuse for modeling and design

prepared by P. Bakowski

Introduction

The arrival of hardware description languages and their standardization is a corner stone for the development of high complexity digital systems. Practically all new digital system designs are done with HDLs. The standardization of VHDLs offered a sure way for the developers of component libraries. The standard component libraries start to play an important role in the design. At the same time the arrival of high level synthesis algorithms and tools gives the possibility to map or to express the VHDL code in structures and the underlying technologies. With the arrival of extensive libraries of synthetizable components (VHDL models), the designer is offered a growing pool of prepared models allowing the design with reuse. This is called also code reusability. The synthesis is a development process based on code/model reusability.

Contents: reusability concept, modeling space cube, generic models, configurable models, exercises

Reusability concept

The reusability is an old mechanism used in many technical domains and in all production process. In the case of electronic systems the same schematic parts like logic gates and registers have been used to construct new digital architectures. More recently however the introduction and the growing usage of VHDL models codified in standard libraries (IEEE-1164, VITAL, ..) offer qualitatively new design environment. There are two complementary aspects of code/model reuse.  The modeling for reuse (MFR) and the design with reuse (DWR). These two aspect are complementary and recursive while the design with reuse may in turn utter reusable models. The ultimate reuse goal is to provide a reuse chain. Such a reuse chain is the only way able to manage the growing complexity of the digital systems.

According to a SEMATECH study ; in 1995 design productivity increased merely 21% while the complexity of designs rose around 50%.

 

Reusable components classification

The reusable component models may be classified along several aspects such as :

Component modeling cube

These three aspects may be represented in the form of modeling space cube.
 

Precision

The degree of detail classifies the components according to the simulation precision. This precision may be complete if the model performs, in terms of behavior and timing, exactly as a real component. For example, the input/output delays must be the same as those in the real component. The precise models can be used as virtual components for the simulated hardware system including the analog features. For the compatible models the functional precision is still required but the timing may be modeled with unitary delays such as clock cycles. The compatible models may be used to simulate the hardware systems with the clock-cycle precision. Finally, the algorithmic models provide no timing information; only the functions are modeled. For example, a model of processor used to validate new instruction set according to a set of programs may be developed at algorithmic level.

Expression

The degree of expression characterizes the depth of the implementation. The hard-blocks are fully expressed models which can be used for fabrication (sign-off models). They carry all the implementation details corresponding to silicon cells used for fabrication. For the VHDL code some additional attributes such as power consumption, cell size should be given in form of attributes. The netlist models are structural descriptions of components built form predefined primitives such as gates, registers, memory blocks, .. . The netlists are expressed from the RTL level VHDL code through the logic synthesis. Finally, the soft blocks are high level descriptions (mainly at RTL), which are synthetizable by higher level synthesis algorithms (tools).

Adaptability

The degree of adaptability or flexibility characterizes the scope of reusability. Closed models cannot be modified before the use; their structure and behavior is fixed forever. If the designer wants to use a closed component, it must adapt the surrounding parts of the system to this component. Generic models tend to be open for the modifications/adaptations concerning the processing width or internal delays. In principle the generic models preserve their initial function provided by the model developer. The configurable models are still more flexible. In addition to the adaptations provided by the generic models, the configurable models offer some degree of functional adaptability through the selection of the appropriate sub-components and their internal architectures. However the external interface of a configurable model stays fixed.
 

Generic code and generic models

Examples of generic models

The generic code may be synthesis oriented, simulation oriented. For the synthesis (expression) oriented models, the generic parameters allow to change some quantitative characteristics such as the width of the busses or processing units, the size of the memory banks, ... For the simulation oriented models we can also provide the changes (adaptations) in the timing characteristics such as inertial and transport delays. In both cases the generic parameters do not modify the component functions. The function or behavior is preserved. However some quantitative parameters of the algorithm may be also generic.
There are three kinds of generic parameters in VHDL:

The timing related generics allow to modify or adapt the temporal behavior of the component model. For example, a simple clock circuit may provide different signal frequency when animated with different period parameter. The content related generics may provide the components with the functional cycles of required length. For example, one can build a modulo N counter , where N is a generic parameter. The structure related generics allows to modify the size of signals and variables in order to provide smaller or bigger structures. For example, a memory block may be instantiated with different word size and different capacity. Still another way to provide the structural modifications/adaptations is to use the generate statement with generic parameters. For example, a counter circuit built from simple flip-flops may be generated in this way. The content and the structure related generics can be applied for simulation as well as for synthetizable models; the timing related generics are valid only for simulation models.

VHDL supports hierarchical modeling . It means that the genericity may also be hierarchical. The higher level modules or components may influence the values of lower level modules or sub-components. However, there is no way to propagate the generic values from lower to higher composition levels. It means that the component must adapt itself to the system; but system cannot adapt itself to the component emanating generic values.

 
 

Configurable code and configurable models

Examples of configurable models

The configurable models allow to build a complex component from a selection of sub-components. These selections may or not modify the way the internal functions are performed. In some extent the functions themselves may be selected from the available pool of component functions. Only the external interface of the configurable component must be fixed. For example one may configure a model to be an up counter or a down counter ; the external interface is still the same.

The selection of sub-components is performed through the configuration statement such as :

for cmpt1: compteur use entity work.counter(up_counter);

where:

  • cmpt1 is an instance of the component
  • compteur is the actual component name
  • counter is entity name
    • the above configuration (selection) statement is integrated into the architecture module
    or
    via a configuration module which is independent of the architecture module

    Exercises