-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\SER_ADD.VHD C:\TEMP\RTL\SER
-- _ADD.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP24.$$$ 
-- Version V2.1.7
-- Definition of  SER_ADD
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 13:02:52 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity SER_ADD is
   port (
      A, B, START, CLOCK : in std_logic ;
      DONE, Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : inout std_logic) ;
end SER_ADD ;

architecture exemplar of SER_ADD is
   signal
      COUNT_0, COUNT_1, COUNT_2, BUSY, CARRY, vh_9, vh_10, vh_11, vh_12, 
      vh_13, vh_14, vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, vh_21, vh_22, 
      vh_23, SUMr1, vh_24, vh_25, vh_26, vh_27, vh_28, vh_29, vh_30, vh_31, 
      vh_32, vh_33, vh_43, vh_44, vh_45, vh_46, vh_50, vh_51, vh_52, vh_56, 
      vh_57, vh_58, vh_59, vh_60, vh_61, vh_62, vh_63, vh_64, vh_65, vh_66, 
      vh_67, vh_68, vh_69, vh_70, vh_71, vh_72, vh_73, vh_74, vh_75, vh_76, 
      vh_77, vh_78, vh_79, vh_104, vh_105, vh_106, vh_110: std_logic ;
 
begin
   vh_9 <= (BUSY) or (START) ;
   vh_10 <= (A and  not B) or ( not A and B) ;
   vh_11 <= (vh_10 and  not CARRY) or ( not vh_10 and CARRY) ;
   vh_12 <= (A and B) ;
   vh_13 <= (A and CARRY) ;
   vh_14 <= (vh_13) or (vh_12) ;
   vh_15 <= (B and CARRY) ;
   vh_16 <= (vh_15) or (vh_14) ;
   vh_17 <= (COUNT_0 and COUNT_1 and COUNT_2) ;
   vh_18 <= (vh_9 and vh_17) ;
   vh_19 <= (vh_9 and vh_17) ;
   vh_20 <= (vh_9 and vh_17) ;
   vh_21 <= (COUNT_0 and  not vh_110) or ( not COUNT_0 and vh_110) ;
   vh_22 <= (COUNT_1 and  not COUNT_2) or ( not COUNT_1 and COUNT_2) ;
   vh_23 <= (vh_9 and  not vh_17) ;
   SUMr1 <= (vh_11 and vh_9) ;
   vh_24 <= (vh_21 and vh_23) ;
   vh_25 <= (vh_22 and vh_23) ;
   vh_26 <= ( not COUNT_2 and vh_23) ;
   vh_27 <= (vh_23) or (vh_18) ;
   vh_28 <= (COUNT_0 and  not vh_27) ;
   vh_29 <= (vh_28) or (vh_24) ;
   vh_30 <= (COUNT_1 and  not vh_27) ;
   vh_31 <= (vh_30) or (vh_25) ;
   vh_32 <= (COUNT_2 and  not vh_27) ;
   vh_33 <= (vh_32) or (vh_26) ;
   vh_43 <= (START and  not vh_20) ;
   vh_44 <= (vh_20) or (START) ;
   vh_45 <= (BUSY and  not vh_44) ;
   vh_46 <= (vh_45) or (vh_43) ;
   vh_50 <= (vh_16 and vh_9) ;
   vh_51 <= (CARRY and  not vh_9) ;
   vh_52 <= (vh_51) or (vh_50) ;
   vh_56 <= (vh_9 and SUMr1) ;
   vh_57 <= (Z_7 and vh_9) ;
   vh_58 <= (Z_6 and vh_9) ;
   vh_59 <= (Z_5 and vh_9) ;
   vh_60 <= (Z_4 and vh_9) ;
   vh_61 <= (Z_3 and vh_9) ;
   vh_62 <= (Z_2 and vh_9) ;
   vh_63 <= (Z_1 and vh_9) ;
   vh_64 <= (Z_7 and  not vh_9) ;
   vh_65 <= (vh_64) or (vh_56) ;
   vh_66 <= (Z_6 and  not vh_9) ;
   vh_67 <= (vh_66) or (vh_57) ;
   vh_68 <= (Z_5 and  not vh_9) ;
   vh_69 <= (vh_68) or (vh_58) ;
   vh_70 <= (Z_4 and  not vh_9) ;
   vh_71 <= (vh_70) or (vh_59) ;
   vh_72 <= (Z_3 and  not vh_9) ;
   vh_73 <= (vh_72) or (vh_60) ;
   vh_74 <= (Z_2 and  not vh_9) ;
   vh_75 <= (vh_74) or (vh_61) ;
   vh_76 <= (Z_1 and  not vh_9) ;
   vh_77 <= (vh_76) or (vh_62) ;
   vh_78 <= (Z_0 and  not vh_9) ;
   vh_79 <= (vh_78) or (vh_63) ;
   vh_104 <= (vh_19) or (START) ;
   vh_105 <= (DONE and  not vh_104) ;
   vh_106 <= (vh_105) or (vh_19) ;
   vh_110 <= (COUNT_1 and COUNT_2) ;
   DFF( vh_29, CLOCK, COUNT_0) ;
   DFF( vh_31, CLOCK, COUNT_1) ;
   DFF( vh_33, CLOCK, COUNT_2) ;
   DFF( vh_46, CLOCK, BUSY) ;
   DFF( vh_52, CLOCK, CARRY) ;
   DFF( vh_65, CLOCK, Z_7) ;
   DFF( vh_67, CLOCK, Z_6) ;
   DFF( vh_69, CLOCK, Z_5) ;
   DFF( vh_71, CLOCK, Z_4) ;
   DFF( vh_73, CLOCK, Z_3) ;
   DFF( vh_75, CLOCK, Z_2) ;
   DFF( vh_77, CLOCK, Z_1) ;
   DFF( vh_79, CLOCK, Z_0) ;
   DFF( vh_106, CLOCK, DONE) ;

end exemplar ;