-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\REG4.VHD C:\TEMP\RTL\REG4.V
-- HD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP23.$$$ 
-- Version V2.1.7
-- Definition of  REG4
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 13:02:32 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity REG4 is
   port (
      D, C, A : in std_logic ;
      Z : out std_logic) ;
end REG4 ;

architecture exemplar of REG4 is
   signal
      FLAGr1, vh_0, vh_1, vh_2: std_logic ;
 
begin
   vh_0 <= (A and D) ;
   vh_1 <= '0' ;
   vh_2 <= '0' ;
   Z <= (FLAGr1 and vh_0) ;
   DFFPC( D, vh_1, vh_2, C, FLAGr1) ;

end exemplar ;