-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\REG2.VHD C:\TEMP\RTL\REG2.V
-- HD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP21.$$$ 
-- Version V2.1.7
-- Definition of  REG2
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 13:01:50 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity REG2 is
   port (
      D, C : in std_logic ;
      Z : out std_logic) ;
end REG2 ;

architecture exemplar of REG2 is
 
begin
   DFF( D, C, Z) ;

end exemplar ;