-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\REG0.VHD C:\TEMP\RTL\REG0.V
-- HD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP19.$$$ 
-- Version V2.1.7
-- Definition of  REG0
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 13:01:07 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity REG0 is
   port (
      S, R : in std_logic ;
      Z : inout std_logic) ;
end REG0 ;

architecture exemplar of REG0 is
   signal
      vh_1, vh_2, vh_3: std_logic ;
 
begin
   Z <= (vh_3) or (S) ;
   vh_1 <= (R and  not S) ;
   vh_2 <= (vh_1) or (S) ;
   vh_3 <= (Z and  not vh_2) ;

end exemplar ;