-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\MACHINE1.VHD C:\TEMP\RTL\MA
-- CHINE1.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP17.$$$ 
-- Version V2.1.7
-- Definition of  MACHINE1
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:59:54 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity MACHINE1 is
   port (
      X, R, CLK : in std_logic ;
      Z : out std_logic) ;
end MACHINE1 ;

architecture exemplar of MACHINE1 is
   signal
      PRESENT_STATE_0, PRESENT_STATE_1, vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, 
      vh_6, vh_7, vh_8, vh_9, vh_11, vh_17, vh_23, vh_24, vh_25, 
      NEXT_STATE_1, NEXT_STATE_0: std_logic ;
 
begin
   vh_0 <= ( not PRESENT_STATE_0 and  not PRESENT_STATE_1) ;
   vh_1 <= (X and vh_0) ;
   vh_2 <= (PRESENT_STATE_0 and  not PRESENT_STATE_1) ;
   vh_3 <= ( not X and vh_2) ;
   vh_4 <= (X and vh_2) ;
   vh_5 <= ( not PRESENT_STATE_0 and PRESENT_STATE_1) ;
   vh_6 <= (X and vh_5) ;
   vh_7 <= (PRESENT_STATE_0 and PRESENT_STATE_1) ;
   vh_8 <= ( not X and vh_7) ;
   vh_9 <= (X and vh_7) ;
   Z <= (PRESENT_STATE_0 and PRESENT_STATE_1) ;
   vh_11 <= '0' ;
   vh_17 <= '0' ;
   vh_23 <= (vh_9) or (vh_6) ;
   vh_24 <= (vh_8) or (vh_6) ;
   vh_25 <= (vh_23) or (vh_4) ;
   NEXT_STATE_1 <= (vh_24) or (vh_3) ;
   NEXT_STATE_0 <= (vh_25) or (vh_1) ;
   DFFPC( NEXT_STATE_0, vh_11, R, CLK, PRESENT_STATE_0) ;
   DFFPC( NEXT_STATE_1, vh_17, R, CLK, PRESENT_STATE_1) ;

end exemplar ;