-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\MACHINE0.VHD C:\TEMP\RTL\MA
-- CHINE0.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP16.$$$ 
-- Version V2.1.7
-- Definition of  MACHINE0
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:59:31 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity MACHINE0 is
   port (
      X, CLK : in std_logic ;
      Z : out std_logic) ;
end MACHINE0 ;

architecture exemplar of MACHINE0 is
   signal
      PRESENT_STATE_0, PRESENT_STATE_1, vh_0, vh_1, vh_2, vh_3, vh_4, vh_5, 
      vh_6, vh_7, vh_8, vh_9, vh_17, vh_18, vh_19, NEXT_STATE_1, 
      NEXT_STATE_0: std_logic ;
 
begin
   vh_0 <= ( not PRESENT_STATE_0 and  not PRESENT_STATE_1) ;
   vh_1 <= (X and vh_0) ;
   vh_2 <= (PRESENT_STATE_0 and  not PRESENT_STATE_1) ;
   vh_3 <= ( not X and vh_2) ;
   vh_4 <= (X and vh_2) ;
   vh_5 <= ( not PRESENT_STATE_0 and PRESENT_STATE_1) ;
   vh_6 <= (X and vh_5) ;
   vh_7 <= (PRESENT_STATE_0 and PRESENT_STATE_1) ;
   vh_8 <= ( not X and vh_7) ;
   vh_9 <= (X and vh_7) ;
   Z <= (PRESENT_STATE_0 and PRESENT_STATE_1) ;
   vh_17 <= (vh_9) or (vh_6) ;
   vh_18 <= (vh_8) or (vh_6) ;
   vh_19 <= (vh_17) or (vh_4) ;
   NEXT_STATE_1 <= (vh_18) or (vh_3) ;
   NEXT_STATE_0 <= (vh_19) or (vh_1) ;
   DFF( NEXT_STATE_0, CLK, PRESENT_STATE_0) ;
   DFF( NEXT_STATE_1, CLK, PRESENT_STATE_1) ;

end exemplar ;