-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\CAO\EXEMPLAR\SYNTHESI\EXAMPLES\ORIGINAL\L
-- OGIC9.VHD C:\TEMP\LOGIC9.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP14.$$$ 
-- 
-- 
-- Version V2.1.7
-- Definition of  LOGIC9
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 13:16:13 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC9 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0, B_7, B_6, B_5, B_4, B_3, B_2, 
      B_1, B_0, C_7, C_6, C_5, C_4, C_3, C_2, C_1, C_0, D_7, D_6, D_5, D_4, 
      D_3, D_2, D_1, D_0, S : in std_logic ;
      Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : out std_logic) ;
end LOGIC9 ;

architecture exemplar of LOGIC9 is
   signal
      BD_7, BD_6, BD_5, BD_4, BD_3, BD_2, BD_1, BD_0, AC_7, AC_6, AC_5, AC_4, 
      AC_3, AC_2, AC_1, AC_0, vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, 
      vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, vh_21, vh_22, vh_23, vh_24, 
      vh_25, vh_26, vh_27, vh_28, vh_29, vh_30, vh_31, vh_32, vh_33, vh_34, 
      vh_35, vh_36, vh_37, vh_38, vh_39, vh_40, vh_41, vh_42, vh_43, vh_44, 
      vh_45, vh_46, vh_47, vh_48, vh_49, vh_50, vh_51, vh_52, vh_53, vh_54, 
      vh_55, vh_56, vh_57, vh_58, vh_59, vh_60, vh_61, vh_62, vh_63, vh_64: 
   std_logic ;
 
begin
   BD_7 <= (vh_16) or (vh_8) ;
   BD_6 <= (vh_17) or (vh_9) ;
   BD_5 <= (vh_18) or (vh_10) ;
   BD_4 <= (vh_19) or (vh_11) ;
   BD_3 <= (vh_20) or (vh_12) ;
   BD_2 <= (vh_21) or (vh_13) ;
   BD_1 <= (vh_22) or (vh_14) ;
   BD_0 <= (vh_23) or (vh_15) ;
   AC_7 <= (vh_32) or (vh_24) ;
   AC_6 <= (vh_33) or (vh_25) ;
   AC_5 <= (vh_34) or (vh_26) ;
   AC_4 <= (vh_35) or (vh_27) ;
   AC_3 <= (vh_36) or (vh_28) ;
   AC_2 <= (vh_37) or (vh_29) ;
   AC_1 <= (vh_38) or (vh_30) ;
   AC_0 <= (vh_39) or (vh_31) ;
   Z_7 <= (AC_7 and  not BD_7 and  not vh_64) or ( not AC_7 and BD_7 and 
       not vh_64) or ( not AC_7 and  not BD_7 and vh_64) or (AC_7 and BD_7
       and vh_64) ;
   Z_6 <= (AC_6 and  not BD_6 and  not vh_60) or ( not AC_6 and BD_6 and 
       not vh_60) or ( not AC_6 and  not BD_6 and vh_60) or (AC_6 and BD_6
       and vh_60) ;
   Z_5 <= (AC_5 and  not BD_5 and  not vh_56) or ( not AC_5 and BD_5 and 
       not vh_56) or ( not AC_5 and  not BD_5 and vh_56) or (AC_5 and BD_5
       and vh_56) ;
   Z_4 <= (AC_4 and  not BD_4 and  not vh_52) or ( not AC_4 and BD_4 and 
       not vh_52) or ( not AC_4 and  not BD_4 and vh_52) or (AC_4 and BD_4
       and vh_52) ;
   Z_3 <= (AC_3 and  not BD_3 and  not vh_48) or ( not AC_3 and BD_3 and 
       not vh_48) or ( not AC_3 and  not BD_3 and vh_48) or (AC_3 and BD_3
       and vh_48) ;
   Z_2 <= (AC_2 and  not BD_2 and  not vh_44) or ( not AC_2 and BD_2 and 
       not vh_44) or ( not AC_2 and  not BD_2 and vh_44) or (AC_2 and BD_2
       and vh_44) ;
   Z_1 <= (AC_1 and  not BD_1 and  not vh_40) or ( not AC_1 and BD_1 and 
       not vh_40) or ( not AC_1 and  not BD_1 and vh_40) or (AC_1 and BD_1
       and vh_40) ;
   Z_0 <= (AC_0 and  not BD_0) or ( not AC_0 and BD_0) ;
   vh_8 <= ( not S and D_7) ;
   vh_9 <= ( not S and D_6) ;
   vh_10 <= ( not S and D_5) ;
   vh_11 <= ( not S and D_4) ;
   vh_12 <= ( not S and D_3) ;
   vh_13 <= ( not S and D_2) ;
   vh_14 <= ( not S and D_1) ;
   vh_15 <= ( not S and D_0) ;
   vh_16 <= (S and B_7) ;
   vh_17 <= (S and B_6) ;
   vh_18 <= (S and B_5) ;
   vh_19 <= (S and B_4) ;
   vh_20 <= (S and B_3) ;
   vh_21 <= (S and B_2) ;
   vh_22 <= (S and B_1) ;
   vh_23 <= (S and B_0) ;
   vh_24 <= ( not S and C_7) ;
   vh_25 <= ( not S and C_6) ;
   vh_26 <= ( not S and C_5) ;
   vh_27 <= ( not S and C_4) ;
   vh_28 <= ( not S and C_3) ;
   vh_29 <= ( not S and C_2) ;
   vh_30 <= ( not S and C_1) ;
   vh_31 <= ( not S and C_0) ;
   vh_32 <= (S and A_7) ;
   vh_33 <= (S and A_6) ;
   vh_34 <= (S and A_5) ;
   vh_35 <= (S and A_4) ;
   vh_36 <= (S and A_3) ;
   vh_37 <= (S and A_2) ;
   vh_38 <= (S and A_1) ;
   vh_39 <= (S and A_0) ;
   vh_40 <= (AC_0 and BD_0) ;
   vh_41 <= (AC_1 and vh_40) ;
   vh_42 <= (AC_1 and BD_1) ;
   vh_43 <= (BD_1 and vh_40) ;
   vh_44 <= (vh_43) or (vh_42) or (vh_41) ;
   vh_45 <= (AC_2 and vh_44) ;
   vh_46 <= (AC_2 and BD_2) ;
   vh_47 <= (BD_2 and vh_44) ;
   vh_48 <= (vh_47) or (vh_46) or (vh_45) ;
   vh_49 <= (AC_3 and vh_48) ;
   vh_50 <= (AC_3 and BD_3) ;
   vh_51 <= (BD_3 and vh_48) ;
   vh_52 <= (vh_51) or (vh_50) or (vh_49) ;
   vh_53 <= (AC_4 and vh_52) ;
   vh_54 <= (AC_4 and BD_4) ;
   vh_55 <= (BD_4 and vh_52) ;
   vh_56 <= (vh_55) or (vh_54) or (vh_53) ;
   vh_57 <= (AC_5 and vh_56) ;
   vh_58 <= (AC_5 and BD_5) ;
   vh_59 <= (BD_5 and vh_56) ;
   vh_60 <= (vh_59) or (vh_58) or (vh_57) ;
   vh_61 <= (AC_6 and vh_60) ;
   vh_62 <= (AC_6 and BD_6) ;
   vh_63 <= (BD_6 and vh_60) ;
   vh_64 <= (vh_63) or (vh_62) or (vh_61) ;

end exemplar ;