-- -- Program -- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\CAO\EXEMPLAR\SYNTHESI\EXAMPLES\ORIGINAL\L -- OGIC8.VHD C:\TEMP\LOGIC8.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP4.$$$ -- -- Version V2.1.7 -- Definition of LOGIC8 -- -- VHDL Concurrent Statements, created by -- Exemplar Logic's CORE -- Fri Nov 17 13:18:59 1995 -- -- -- library exemplar ; use exemplar.exemplar_1164.all ; library ieee ; use ieee.std_logic_1164.all ; entity LOGIC8 is port ( A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0, B_7, B_6, B_5, B_4, B_3, B_2, B_1, B_0, C_7, C_6, C_5, C_4, C_3, C_2, C_1, C_0, D_7, D_6, D_5, D_4, D_3, D_2, D_1, D_0, S : in std_logic ; Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1, Z_0 : out std_logic) ; end LOGIC8 ; architecture exemplar of LOGIC8 is signal vh_8, vh_9, vh_10, vh_11, vh_12, vh_13, vh_14, vh_15, vh_16, vh_17, vh_18, vh_19, vh_20, vh_21, vh_22, vh_23, vh_24, vh_25, vh_26, vh_27, vh_28, vh_29, vh_30, vh_31, vh_32, vh_33, vh_34, vh_35, vh_36, vh_37, vh_38, vh_39, vh_40, vh_41, vh_42, vh_43, vh_44, vh_45, vh_46, vh_47, vh_48, vh_49, vh_50, vh_51, vh_52, vh_53, vh_54, vh_55, vh_56, vh_57, vh_58, vh_59, vh_60, vh_61, vh_62, vh_63, vh_64, vh_65, vh_66, vh_67, vh_68, vh_69, vh_70, vh_71, vh_72, vh_73, vh_74, vh_75, vh_76, vh_77, vh_78, vh_79, vh_80, vh_81, vh_82, vh_83, vh_84, vh_85, vh_86, vh_87, vh_88, vh_89: std_logic ; begin Z_7 <= (vh_32) or (vh_24) ; Z_6 <= (vh_33) or (vh_25) ; Z_5 <= (vh_34) or (vh_26) ; Z_4 <= (vh_35) or (vh_27) ; Z_3 <= (vh_36) or (vh_28) ; Z_2 <= (vh_37) or (vh_29) ; Z_1 <= (vh_38) or (vh_30) ; Z_0 <= (vh_39) or (vh_31) ; vh_8 <= (C_7 and not D_7 and not vh_64) or ( not C_7 and D_7 and not vh_64) or ( not C_7 and not D_7 and vh_64) or (C_7 and D_7 and vh_64) ; vh_9 <= (C_6 and not D_6 and not vh_60) or ( not C_6 and D_6 and not vh_60) or ( not C_6 and not D_6 and vh_60) or (C_6 and D_6 and vh_60) ; vh_10 <= (C_5 and not D_5 and not vh_56) or ( not C_5 and D_5 and not vh_56) or ( not C_5 and not D_5 and vh_56) or (C_5 and D_5 and vh_56) ; vh_11 <= (C_4 and not D_4 and not vh_52) or ( not C_4 and D_4 and not vh_52) or ( not C_4 and not D_4 and vh_52) or (C_4 and D_4 and vh_52) ; vh_12 <= (C_3 and not D_3 and not vh_48) or ( not C_3 and D_3 and not vh_48) or ( not C_3 and not D_3 and vh_48) or (C_3 and D_3 and vh_48) ; vh_13 <= (C_2 and not D_2 and not vh_44) or ( not C_2 and D_2 and not vh_44) or ( not C_2 and not D_2 and vh_44) or (C_2 and D_2 and vh_44) ; vh_14 <= (C_1 and not D_1 and not vh_40) or ( not C_1 and D_1 and not vh_40) or ( not C_1 and not D_1 and vh_40) or (C_1 and D_1 and vh_40) ; vh_15 <= (C_0 and not D_0) or ( not C_0 and D_0) ; vh_16 <= (A_7 and not B_7 and not vh_89) or ( not A_7 and B_7 and not vh_89) or ( not A_7 and not B_7 and vh_89) or (A_7 and B_7 and vh_89) ; vh_17 <= (A_6 and not B_6 and not vh_85) or ( not A_6 and B_6 and not vh_85) or ( not A_6 and not B_6 and vh_85) or (A_6 and B_6 and vh_85) ; vh_18 <= (A_5 and not B_5 and not vh_81) or ( not A_5 and B_5 and not vh_81) or ( not A_5 and not B_5 and vh_81) or (A_5 and B_5 and vh_81) ; vh_19 <= (A_4 and not B_4 and not vh_77) or ( not A_4 and B_4 and not vh_77) or ( not A_4 and not B_4 and vh_77) or (A_4 and B_4 and vh_77) ; vh_20 <= (A_3 and not B_3 and not vh_73) or ( not A_3 and B_3 and not vh_73) or ( not A_3 and not B_3 and vh_73) or (A_3 and B_3 and vh_73) ; vh_21 <= (A_2 and not B_2 and not vh_69) or ( not A_2 and B_2 and not vh_69) or ( not A_2 and not B_2 and vh_69) or (A_2 and B_2 and vh_69) ; vh_22 <= (A_1 and not B_1 and not vh_65) or ( not A_1 and B_1 and not vh_65) or ( not A_1 and not B_1 and vh_65) or (A_1 and B_1 and vh_65) ; vh_23 <= (A_0 and not B_0) or ( not A_0 and B_0) ; vh_24 <= ( not S and vh_8) ; vh_25 <= ( not S and vh_9) ; vh_26 <= ( not S and vh_10) ; vh_27 <= ( not S and vh_11) ; vh_28 <= ( not S and vh_12) ; vh_29 <= ( not S and vh_13) ; vh_30 <= ( not S and vh_14) ; vh_31 <= ( not S and vh_15) ; vh_32 <= (S and vh_16) ; vh_33 <= (S and vh_17) ; vh_34 <= (S and vh_18) ; vh_35 <= (S and vh_19) ; vh_36 <= (S and vh_20) ; vh_37 <= (S and vh_21) ; vh_38 <= (S and vh_22) ; vh_39 <= (S and vh_23) ; vh_40 <= (C_0 and D_0) ; vh_41 <= (C_1 and vh_40) ; vh_42 <= (C_1 and D_1) ; vh_43 <= (D_1 and vh_40) ; vh_44 <= (vh_43) or (vh_42) or (vh_41) ; vh_45 <= (C_2 and vh_44) ; vh_46 <= (C_2 and D_2) ; vh_47 <= (D_2 and vh_44) ; vh_48 <= (vh_47) or (vh_46) or (vh_45) ; vh_49 <= (C_3 and vh_48) ; vh_50 <= (C_3 and D_3) ; vh_51 <= (D_3 and vh_48) ; vh_52 <= (vh_51) or (vh_50) or (vh_49) ; vh_53 <= (C_4 and vh_52) ; vh_54 <= (C_4 and D_4) ; vh_55 <= (D_4 and vh_52) ; vh_56 <= (vh_55) or (vh_54) or (vh_53) ; vh_57 <= (C_5 and vh_56) ; vh_58 <= (C_5 and D_5) ; vh_59 <= (D_5 and vh_56) ; vh_60 <= (vh_59) or (vh_58) or (vh_57) ; vh_61 <= (C_6 and vh_60) ; vh_62 <= (C_6 and D_6) ; vh_63 <= (D_6 and vh_60) ; vh_64 <= (vh_63) or (vh_62) or (vh_61) ; vh_65 <= (A_0 and B_0) ; vh_66 <= (A_1 and vh_65) ; vh_67 <= (A_1 and B_1) ; vh_68 <= (B_1 and vh_65) ; vh_69 <= (vh_68) or (vh_67) or (vh_66) ; vh_70 <= (A_2 and vh_69) ; vh_71 <= (A_2 and B_2) ; vh_72 <= (B_2 and vh_69) ; vh_73 <= (vh_72) or (vh_71) or (vh_70) ; vh_74 <= (A_3 and vh_73) ; vh_75 <= (A_3 and B_3) ; vh_76 <= (B_3 and vh_73) ; vh_77 <= (vh_76) or (vh_75) or (vh_74) ; vh_78 <= (A_4 and vh_77) ; vh_79 <= (A_4 and B_4) ; vh_80 <= (B_4 and vh_77) ; vh_81 <= (vh_80) or (vh_79) or (vh_78) ; vh_82 <= (A_5 and vh_81) ; vh_83 <= (A_5 and B_5) ; vh_84 <= (B_5 and vh_81) ; vh_85 <= (vh_84) or (vh_83) or (vh_82) ; vh_86 <= (A_6 and vh_85) ; vh_87 <= (A_6 and B_6) ; vh_88 <= (B_6 and vh_85) ; vh_89 <= (vh_88) or (vh_87) or (vh_86) ; end exemplar ;