-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\CAO\EXEMPLAR\SYNTHESI\EXAMPLES\ORIGINAL\L
-- OGIC7.VHD C:\TEMP\LOGIC7.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP12.$$$ 
-- 
-- 
-- Version V2.1.7
-- Definition of  LOGIC7
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 13:15:28 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC7 is
   port (
      A_7, A_6, A_5, A_4, A_3, A_2, A_1, A_0 : in std_logic ;
      Z_7, Z_6, Z_5, Z_4, Z_3, Z_2, Z_1 : inout std_logic ;
      N_2, N_1, N_0, Z_0, F : out std_logic) ;
end LOGIC7 ;

architecture exemplar of LOGIC7 is
   signal
      vh_1, vh_3, vh_5, vh_7, vh_9, vh_11, vh_13, vh_14, vh_15, vh_16, vh_17, 
      vh_18, vh_19, vh_20, vh_21, vh_22, vh_23, vh_24, vh_25, vh_26, vh_27, 
      vh_28, vh_29, vh_30, vh_31, vh_33, vh_34, vh_35, vh_36, vh_37, vh_38, 
      vh_39, vh_40, vh_41, vh_42, vh_43, vh_45, vh_46, vh_47, vh_48, vh_49, 
      vh_50, vh_51, vh_53, vh_54: std_logic ;
 
begin
   Z_1 <= (A_1 and  not A_0) ;
   vh_1 <= ( not A_1 and  not A_0) ;
   Z_2 <= (A_2 and vh_1) ;
   vh_3 <= ( not A_2 and vh_1) ;
   Z_3 <= (A_3 and vh_3) ;
   vh_5 <= ( not A_3 and vh_3) ;
   Z_4 <= (A_4 and vh_5) ;
   vh_7 <= ( not A_4 and vh_5) ;
   Z_5 <= (A_5 and vh_7) ;
   vh_9 <= ( not A_5 and vh_7) ;
   Z_6 <= (A_6 and vh_9) ;
   vh_11 <= ( not A_6 and vh_9) ;
   Z_7 <= (A_7 and vh_11) ;
   vh_13 <= (Z_6 and  not Z_7) ;
   vh_14 <= (vh_13) or (Z_7) ;
   vh_15 <= (Z_7) or (Z_6) ;
   vh_16 <= (Z_5 and  not vh_15) ;
   vh_17 <= (vh_16) or (vh_14) ;
   vh_18 <= (Z_5) or (vh_15) ;
   vh_19 <= (Z_4 and  not vh_18) ;
   vh_20 <= (vh_19) or (vh_17) ;
   vh_21 <= (Z_4) or (vh_18) ;
   vh_22 <= (Z_3 and  not vh_21) ;
   vh_23 <= (vh_22) or (vh_20) ;
   vh_24 <= (Z_3) or (vh_21) ;
   vh_25 <= (Z_2 and  not vh_24) ;
   vh_26 <= (vh_25) or (vh_23) ;
   vh_27 <= (Z_2) or (vh_24) ;
   vh_28 <= (Z_1 and  not vh_27) ;
   vh_29 <= (vh_28) or (vh_26) ;
   vh_30 <= (Z_1) or (vh_27) ;
   vh_31 <= (A_0 and  not vh_30) ;
   F <= (vh_31) or (vh_29) ;
   vh_33 <= (Z_6 and  not Z_7) ;
   vh_34 <= (vh_33) or (Z_7) ;
   vh_35 <= (Z_6 and  not Z_7) ;
   vh_36 <= (vh_35) or (Z_7) ;
   vh_37 <= (Z_7) or (Z_6) ;
   vh_38 <= (Z_5 and  not vh_37) ;
   vh_39 <= (vh_38) or (vh_34) ;
   vh_40 <= (Z_5 and  not vh_37) ;
   vh_41 <= (vh_40) or (Z_7) ;
   vh_42 <= (Z_5) or (vh_37) ;
   vh_43 <= (Z_4 and  not vh_42) ;
   N_2 <= (vh_43) or (vh_39) ;
   vh_45 <= (Z_4) or (vh_42) ;
   vh_46 <= (Z_3 and  not vh_45) ;
   vh_47 <= (vh_46) or (vh_36) ;
   vh_48 <= (Z_3 and  not vh_45) ;
   vh_49 <= (vh_48) or (vh_41) ;
   vh_50 <= (Z_3) or (vh_45) ;
   vh_51 <= (Z_2 and  not vh_50) ;
   N_1 <= (vh_51) or (vh_47) ;
   vh_53 <= (Z_2) or (vh_50) ;
   vh_54 <= (Z_1 and  not vh_53) ;
   N_0 <= (vh_54) or (vh_49) ;
   Z_0 <= A_0 ;

end exemplar ;