-- 
-- Program 
-- C:\CAO\EXEMPLAR\BIN\PC\FPGA.EXE C:\TEMP\ORIGINAL\LOGIC3.VHD C:\TEMP\RTL\LOGI
-- C3.VHD -COMMAND_FILE=C:\CAO\EXEMPLAR\BIN\PC\TMP11.$$$ 
-- Version V2.1.7
-- Definition of  LOGIC3
-- 
-- VHDL Concurrent Statements, created by
-- Exemplar Logic's CORE
--      Fri Nov 17 12:55:56 1995
-- 
-- 
-- 

library exemplar ;
use exemplar.exemplar_1164.all ;
library ieee ;
use ieee.std_logic_1164.all ;

entity LOGIC3 is
   port (
      BCD_IN_3, BCD_IN_2, BCD_IN_1, BCD_IN_0 : in std_logic ;
      SSD_OUT_4 : inout std_logic ;
      SSD_OUT_6, SSD_OUT_5, SSD_OUT_3, SSD_OUT_2, SSD_OUT_1, SSD_OUT_0
       : out std_logic) ;
end LOGIC3 ;

architecture exemplar of LOGIC3 is
   signal
      vh_7, vh_8, vh_9: std_logic ;
 
begin
   SSD_OUT_6 <= ( not BCD_IN_0) or (BCD_IN_2) or (BCD_IN_3) ;
   SSD_OUT_5 <= ( not BCD_IN_3 and  not BCD_IN_2 and  not BCD_IN_0) or (
       not BCD_IN_3 and vh_7) or ( not vh_8) ;
   SSD_OUT_4 <= ( not vh_8) or ( not BCD_IN_3) ;
   SSD_OUT_3 <= (vh_9) or ( not BCD_IN_0) ;
   SSD_OUT_2 <= (BCD_IN_2 and BCD_IN_1 and  not BCD_IN_0) or ( not BCD_IN_0
       and  not vh_8) or ( not SSD_OUT_4) ;
   SSD_OUT_1 <= ( not BCD_IN_0 and  not vh_8) or (BCD_IN_2 and  not vh_7)
       or (BCD_IN_3) ;
   SSD_OUT_0 <= (BCD_IN_1 and  not BCD_IN_0) or (vh_9) ;
   vh_7 <= ( not BCD_IN_1 and  not BCD_IN_0) or (BCD_IN_1 and BCD_IN_0) ;
   vh_8 <= (BCD_IN_1) or (BCD_IN_2) ;
   vh_9 <= (BCD_IN_2 and  not BCD_IN_1) or (BCD_IN_3) ;

end exemplar ;